uc3856

UC1856

UC2856

UC3856

Improved Current Mode PWM Controller

FEATURESDESCRIPTION

• Pin-for-Pin Compatible With the UC3846The UC3856 is a high performance version of the popular UC3846

•65ns Typical Delay From Shutdown to

Outputs, and 50ns Typical Delay From

Sync to Outputs

Improved Current Sen Amplifier With•

Reduced Noi Sensitivity

Differential Current Sen with 3V•

Common Mode Range

Trimmed Oscillator Discharge Current•

for Accurate Deadband Control

Accurate 1V Shutdown Threshold•

High Current Dual Totem Pole Outputs•

(1.5A peak)

TTL Compatible Oscillator SYNC Pin•

Thresholds

4kV ESD Protection•

ries of current mode controllers, and is intended for both design

upgrades and new applications where speed and accuracy are impor-

tant.All input to output delays have been minimized, and the current

n output is slew rate limited to reduce noi nsitivity.Fast 1.5A

peak output stages have been added to allow rapid switching of

power FETs.

A low impedance TTL compatible sync output has been implemented

with a tri-state function when ud as a sync input.

Internal chip grounding has been improved to minimize internal

“noi”caud when driving large capacitive loads.This, in conjunc-

tion with the improved differential current n amplifier results in

enhanced noi immunity.

Other features include a trimmed oscillator current (8%) for accurate

frequency and dead time control;a 1V, 5% shutdown threshold;and

4kV minimum ESD protection on all pins.

BLOCK DIAGRAM

UDG-96176

9/96

UC1856

UC2856

UC3856

ABSOLUTE MAXIMUM RATINGS

+40V

Collector +40V

Output Current, Source or Sink

DC...................................................................................0.5A

Pul (0.5µs)...................................................................2.0A

Error −0.3V to +V

IN

−0.3V to +10V

Current −0.3V to +3V

SYNC ±10mA

Error Amplifier −5mA

Soft Start 50mA

Oscillator 5mA

Power Dissipation at T=25°C (Note 2).......................1000mW

A

Power Dissipation at T=25°C (Note 2)......................2000mW

C

Junction T−55°C to +150°C

Storage T−65°C to +150°C

Lead Temperature (Soldering, 10 c.)...........................+300°C

All voltages are with respect to Ground.Currents are positive

into, negative out of the specified terminal.Consult packaging

ction of databook for thermal limitations and considerations of

package.

PLCC-28 (Top View)

QP PACKAGE

CONNECTION DIAGRAMS

DIL–16,SOIC-16 (Top View)

J or N,DW PACKAGE

PLCC-20 (Top View)

Q PACKAGE

UC1856;−40°C to +85°C for the UC2856;and 0°C to +70°C for the UC3856, VIN

== = =

15V, RT 10k, CT 1nF, TT.

AJ

PARAMETERTEST CONDITIONSMINTYP MAXMINTYPMAXUNITS

Reference Section

Output VoltageT=25°C, Io =1mA5.055.105.155.005.105.20V

Line RegulationVIN =8V to 40V2020mV

Load RegulationIo =−1mA to −10mA1515mV

Total Output VariationLine, Load, and Temperature5.205.25V5.004.95

Output Noi Voltage10Hz < f < 10kHz, T=25°CµV5050

Long Term StabilityT=125°C, 1000 Hrs (Note 2)2525mV55

Short Circuit CurrentVREF=0V−65−65mA−45−45−25−25

Oscillator Section

Initial AccuracyT=25°C220220kHz200200180180

J

J

J

J

Over Operating Range230230kHz170170

UC1856/UC2856UC3856

ELECTRICAL CHARACTERISTICS

Unless otherwi stated, the specifications apply for T−55°C to +125°C for

A

=

2

UC1856

UC2856

UC3856

ELECTRICAL CHARACTERISTICS (cont.)

Unless otherwi stated, the specifications apply for T−55°C to

A

=

UC1856/UC2856UC3856

MINTYP MAXPARAMETERTEST CONDITIONSMINTYPMAXUNITS

2Voltage StabilityVIN=8V to 40V2%

8.8Discharge CurrentT=25°C, V=2V8.8mA7.58.07.58.0

8.8V=2V8.8mA6.78.06.78.0

0.4Sync Output Low LevelIo =+1mA0.4V0.20.2

2.0Sync Input High LevelCT =0V, RT =VREFV2.01.51.5

0.8Sync Input Low LevelCT =0V, RT =VREF0.8V1.51.5

10Sync Input CurrentCT =0V, RT =VREF10µA11

100Sync Delay to OutputsCT =0V, RT =VREF100ns5050

+125°C for UC1856;−40°C to +85°C for the UC2856;and 0°C to +70°C for the UC3856, VIN

== = =

15V, RT 10k, CT 1nF, TT.

AJ

Oscillator Section (cont.)

Sync Output High LevelIo =−1mAV2.43.62.43.6

Error Amplifier Section

Input Offt VoltageV=2V510mV

Input Bias Current−1−1µA

Input Offt Current500500nA

Common Mode RangeVIN=8V to 40V0VIN − 20VIN − 2V

Open Loop GainVo =1.2V to 3V8010080100dB

Unity Gain BandwidthT=25°C11.511.5MHz

CMRRV=0V to 38V, VIN= 40V7510075100dB

PSRRVIN=8V to 40V8010080100dB

Output Sink CurrentV=−15mV, Vc= 1.2V510510mA

Output Source CurrentV=15mV, V2.5V−0.4−0.5−0.4−0.5mA

Output High LevelV=50mV, R(COMP) 15k4.34.64.94.34.64.9V

Output Low LevelV=−50mV, R(COMP) 15k0.710.71V

Current Sen Amplifier Section

Amplifier Gain V−=0V, CL SS Open (Notes 3,4)2.753.02.753.0V/V2.52.5

Maximum DifferentialCL SSOpen(Note 3)1.21.2V1.11.1

Input Signal (V+−Vcs-)R(COMP) =15k

CSL

Input Offt VoltageV

CMRRV=0V to 3VdB6060

PSRRVIN =8V to 40VdB6060

Input Bias Current V=0.5V, COMP Open (Note 3)µA−1−3−1−3

Input Offt CurrentV=0.5V, COMP Open (Note 3)mA11

Input Common Mode RangeV3003

Delay to OutputsV

Current Limit Adjust Section

Current Limit Offt V

Input Bias Current V+=VREF, V−=0V−10−30−10−30µA

Shutdown Terminal Section

Threshold Voltage1.051.05V0.951.000.951.00

Input Voltage Range55V00

JCT

CT

V=5V

SYNC

V=0.8V to 2V

SYNC

CM

J

CM

IDOMP

IDCOMP

=

IDL

=

IDL

=

CS

CLSS

= 0.5V535535mV

COMPOpen (Note 3)

CM

CLSS

CLSS

EA

+=VREF, EA−=0Vns250120120250

CS+ −CS−=0V to 1.5V

CS

- = 0V0.430.50.570.430.50.57V

V+= 0V, COMP = Open (Note 3)

CS

EAEA

3

UC1856

UC2856

UC3856

+125°C for UC1856;−40°C to +85°C for the UC2856;and 0°C to +70°C for the UC3856, VIN

== = =

15V, RT 10k, CT 1nF, TT.

AJ

PARAMETERTEST CONDITIONSMINTYP MAXMINTYPMAXUNITS

Shutdown Terminal Section (cont.)

Minimum Latching(Note 5)31.531.5mA

Current (I)

CLSS

Maximum Non-Latching(Note 6)1.50.81.50.8mA

Current (I)

CLSS

Delay to OutputsV=0 to 1.3V6511065110ns

Output Section

Collector-Emitter Voltage4040V

Off-State Bias CurrentVC =40V 250250µA

Output Low LevelI=20mA0.10.50.10.5V

Output High LevelI=−20mA12.513.213.2V12.5

OUT

I=200mA0.52.60.52.6V

OUT

OUT

I=−200mA1213.113.1V12

OUT

C1 =1nF408040nsRi Time 80

C1 =1nF408040nsFall Time80

VIN =0V, I20mA0.81.50.8VUVLO Low Saturation1.5

OUT

=

%Maximum Duty Cycle454750454750

%Minimum Duty Cycle00

VStartup Threshold7.78.07.78.0

VThreshold Hysterisis0.70.7

mASupply Current18231823

SHUTDOWN

UC1856/UC2856UC3856

ELECTRICAL CHARACTERISTICS (cont.)

Unless otherwi stated, the specifications apply for T−55°C to

A

=

PWM Section

Undervoltage Lockout Section

Total Standby Current

Note 1:All voltages are with respect to GND.Currents are positive into, negative out of the specified terminal.

Note 2:This parameter, although guaranteed over the recommended operating conditions is not 100% tested in production.

Note 3:Parameter measured at trip point of latch with V

EAEA

+ VREF, V0V.

=-=

Note 4:Amplifier gain defined as:

∆

V

COMP

G ;V0V to 1.0V

=∆−=

CS

∆

V+

CS

Note 5:Current into CL SS guaranteed to latch circuit into shutdown state.

Note 6:Current into CL SS guaranteed not to latch circuit into shutdown state.

4

UC1856

UC2856

UC3856

APPLICATIONS INFORMATION

Oscillator Circuit

2C

T

Output deadtime is determined by size of the external capacitor, C, according to the formula:Td =

T

3.6

8mA −........

For large values of R

TT

:Td =250C

R

T

2

Oscillator frequency is approximated by the formula:f=

T

RC

TT

UDG-96177

Error Amplifier Output Configuration

Error Amplifier Gain and Pha vs Frequency

O

P

E

N

-

L

O

O

P

V

O

L

T

A

G

E

G

A

I

N

(

d

B

)

80

60

40

20

0

V=20V

IN

o

T=25

J

1001k10k100k1M

-90

o

-180

o

OPEN-LOOP PHASE

0

o

Error Amplifier can source up to 0.5mA.

UDG-96178UDG-96179

FREQUENCY (Hz)

Error Amplifier Open-Loop D.C.Gain vs

Load Resistance

O

P

E

N

-

L

O

O

P

V

O

L

T

A

G

E

G

A

I

N

(

d

B

)

110

V=20V

IN

o

T25

J

=

100

90

80

70

0102030405060708090100

UDG-96180

OUTPUT LOAD RESISTANCE R (k-OHMS)

L

5

UC1856

UC2856

UC3856

APPLICATIONS INFORMATION (cont.)

Parallel Operation

Slaving allows parallel operation of two or more units with equal current sharing.

UDG-96181

Pul by Pul Current Limiting

Peak current (I) is determined by the formula:I=

SS

R2 V

−0.5

( )

R1 + R2

REF

3R

S

UDG-96182

6

UC1856

UC2856

UC3856

APPLICATIONS DATA (cont.)

UDG-96183

UDG-96184

V

REF

If <0.8mA, the shutdown latch will commutate

R1

when I

SS

=0.8mA and a restart cycle will be initiated.

V

REF

If <3mA, the device will latch off until power is

R1

recycled.

Current Sen Amplifier Connections

A small RC filter may be required in some applications to reduce switch transients.

Differential input allows remote, noi nsing.

7

UDG-96185

UC1856

UC2856

UC3856

APPLICATIONS INFORMATION (cont.)

UC1856 Open Loop Test Circuit

- BYPASS CAPS SHOULD BE LOW ESR & ESL TYPE

- SHORT E/A- & COMP FOR UNITY GAIN TESTING

THE USE OF A GROUND PLANE IS HIGHLY RECOMMENDED

UDG-96186

UNITRODE INTEGRATED CIRCUITS

7 CONTINENTAL BLVD.• MERRIMACK, NH 03054

TEL.603-424-2410 • FAX 603-424-3460

8

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