Chapter 4:TriMatrix Embedded Memory Blocks in Stratix III Devices
Clocking Modes
Clocking Modes
Stratix III TriMatrix memory blocks support the following clocking modes:
■Independent
■Input/output
■Read/write
■Single clock
1Violating the tup or hold time on the memory block address registers could corrupt the memory contents. This applies to both read and write operations.
1Altera recommends using a memory block clock that comes through global clock routing from an on-chip PLL t to 50% output duty cycle to achieve the maximum
memory block performance. U Quartus II to report timing for this and other
memory block clocking schemes.
f For more 法国革命
information refer to the Stratix III Device Family Errata Sheet.
Table4–9 shows the clocking mode versus memory mode support matrix.
Table4–9.Stratix III TriMatrix Memory Clock Modes
Independent Clock Mode
Stratix III TriMatrix memory blocks can implement independent clock mode for true
dual-port memories. In this mode, a parate clock is available for each port (A and
B). Clock A controls all registers on the port A side, while clock B controls all registers
on the port B side. Each port also supports independent clock enables for port A and
port B registers. Asynchronous clears are supported only for output latches and
output registers on both ports.
Input/Output Clock Mode
Stratix III TriMatrix memory blocks can implement input/output clock mode for true
and simple dual-port memories. In this mode, an input clock controls all registers
related to the兰花指歌词
data input to the memory block, including data, address, byte-enables,
read enables, and write enables. An output clock controls the data output registers.
Asynchronous clears are available on output latches and output registers only.
Chapter 4:TriMatrix Embedded Memory Blocks in Stratix III Devices
Design Considerations
Read/Write Clock Mode
Stratix III TriMatrix memory blocks can implement read/write clock mode for simple
dual-port memories. In this mode, a write clock controls the data-input,
write-address, and write-enable registers. Similarly, a read clock control the
data-output, read-address, and read-enable registers. The memory blocks support
independent clock enables for both the read and write clocks. Asynchronous clears
are available on data output latches and registers only.
When using read/write mode, if you perform a simultaneous read/write to the same
address location, the output read data will be unknown. If you require the output data
to be a known value in this ca, u either single-clock mode or input/output clock
mode and choo the appropriate read-during-write behavior in the Megawizard.
Single Clock Mode
Stratix III TriMatrix memory blocks can implement single-clock mode for true
dual-port, simple dual-port, and single-port memories. In this mode, a single clock,
together with a clock enable, is ud to control all registers of the memory block.
Asynchronous clears are available公务员考核
on output latches and output registers only.
Design Considerations
This ction describes guidelines for designing with TriMatrix memory blocks.
Selecting TriMatrix Memory Blocks
The Quartus II software automatically partitions ur-defined memory into
embedded memory blocks by taking into account both speed and size constraints
placed on your design. For example, the Quartus II software may spread out a
memory across multiple memory blocks when resources are available to increa the
performance of the design. You can manually assign the memory to a specific block
size via the RAM MegaWizard Plug-In Manager.
MLABs can implement single-port SRAM through e女朋友的英文
mulation via the Quartus II
software. Emulation results 作业答案大全
in minima元旦诗词
l additional logic resources being ud. Becau
of the dual-purpo architecture of the MLAB, it only has data input registers and
output registers in the block. MLABs gain input address registers and additional
optional data output registers from adjacent ALMs by using register packing.
f For more information about register packing, refer to the Logic Array Blocks and
Adaptive Logic Modules in Stratix III Devices chapter in volume 1 of the Stratix III Device
Handbook.
Conflict Resolution
When using the memory blocks in true dual-port mode, it is possible to attempt two
write operations to the same memory location (address). Since no conflict resolution
circuitry is built into the memory blocks, this results in unknown data being written to
that location. Therefore, you must implement conflict resolution logic external to the
memory block to avoid address co勾魂美女
nflicts.
xxiv List of Tables
Section I: Device Core
Revision History
Chapter 5:DSP Blocks in Stratix III Devices
Operational Mode Descriptions
The cond-stage and output registers are triggered by the positive edge of the clock
signal and are cleared on power up. The following DSP block signals control the
output registers within the DSP block:
■clock[3..0]
■ena[3..0]
■aclr[3..0]
Operational Mode Descriptions
The various modes of operation are discusd below.
Independent Multiplier Modes
In independent input and output multiplier mode, the DSP block performs individual
multiplication operations for general-purpo multipliers.
9-, 12-, and 18-Bit Multiplier
You can configure each DSP block multiplier fo有耐心的
r 9-, 12-, or 18-bit multiplication. A
single DSP block can support up to eight最喜欢的英文
individual 99 multipliers, six 1212
multipliers, or up to four individual 1818 multipliers. For operand widths up to
9bits, a 99 multiplier is implemented. For operand widths from 10 to 12 bits, a
1212 multiplier is implemented, and for operand widths from 13 to 18 bits, an
1818 multiplier is implemented. This is done by the Quartus II software by
zero-padding the LSBs. Figure5–8, Figure5–9, and Figure5–10 show the DSP block in
the independent multiplier operation mode.
Figure5–8.18-Bit Independent Multiplier Mode for Half-DSP Block
w
resul我的家人英语作文
t_0[ ]
data b
data b
