A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers
William S.T.Yan and Howard C.Luong ,Member,IEEE
Abstract—A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is prented.Implemented in a
0.5-121.8dBc/Hz at 600-kHz offt,and the mea-sured spurious levels are
82.0dBc at 1.6and 11.3MHz offt,respectively.
Index Terms—Frequency synthesis,frequency synthesizer,pha-locked loop,radio frequency,voltage-controlled oscillator.
I.I NTRODUCTION
M
ODERN transceivers for wireless communication con-sist of low-noi amplifiers,power amplifiers,mixers,DSP chips,filters,and frequency synthesizers.The building blocks have been realized using hybrid technologies and require interfacing circuits,which increas the power consumption and limits the maximum operating speed of the transceivers.For this reason,it has become increasingly attractive to design and monolithically integrate all the building blocks on a single chip.
Designing fully integrated frequency synthesizers for this in-tegration is always desirable but most challenging.The first requirement is to achieve high-frequency operation with rea-sonable power con
sumption.However,the most critical chal-lenges for the frequency synthesizer are the pha-noi and spurious-level performance.Finally,small chip area is esntial to monolithic system integration.
In recent years,monolithic frequency synthesizers with good pha-noi performance have been reported [1]–[3].However,tho designs operate at supply voltages of at least 2.7V and power consumption of more than 50mW.Moreover,
fractional-frequency synthesizers suffer from fractional spurs which degrade their spurious-tone performance.
This paper prents a monolithic dual-loop frequency synthesizer for GSM 900system,which is implemented in a
0.5-121.8dBc/Hz at 600kHz),low spurious level
(
s).Section II derives the design specification of the frequency synthesizer for GSM 900.Section III describes the archi-tecture for the propod dual-loop design.In Section IV ,
Manuscript received December 29,1999;revid October 5,2000.
The authors are with the Department of Electrical and Electronic Engineering,Hong Kong University of Science and Technology,Clear Water Bay,Kowloon,Hong Kong (e-mail:eetak@ee.ust.hk;eeluong@ee.ust.hk).Publisher Item Identifier S
0018-9200(01)00927-1.
Fig.1.Block diagram of the GSM-receiver front-end.
circuit implementation of critical building blocks is discusd.Section V prents the measurement results of the synthesizer including its pha noi,spurious level,and switching time of the frequency synthesizer together with a comprehensive performance evaluation.
II.D ESIGN S PECIFICATION
The performance of frequency synthesizers is mainly speci-fied by their output frequency,pha noi,spurious level,and switching time.This ction derives the specifications of a fre-quency synthesizer for GSM receivers.A.Output Frequency
In GSM-900systems,the receiver-channel frequencies are expresd as
follows:
)of 70MHz for ba-band signal
processing.To extract information from the desired channel,the
local oscillator (LO)output frequency
(
society是什么意思)of the frequency synthesizer is changed accordingly,as
follows:
Fig.2.SNR degradation due to the pha noi and spurious level.
as
43dBm[4].With a correct LO frequency,the desired channel signal is downconverted to IF frequency.However,blocking signals are also downconverted with the LO signal and its pha noi.Since the power of the blocking signal is much larger than that of the desired signal, the pha-noi power falls into the IF frequency and degrades the signal to noi ratio(SNR).The pha-noi
specification
jnkdBc/Hz at600kHz(3)
where SNR of9dB is the SNR specification for the whole
receiver,
and
can be expresd as
follows:
s.
However,to take care of the ttling time of the other compo-
nents,the switching time of the frequency synthesizer is recom-
mended to be kept within one time slot
(577
Fig.4.Propod dual-loop frequency synthesizer.
Due to the dual-loop architecture,the comparison frequen-cies of the low-frequency and high-frequency loops are scaled up from 200kHz to 1.6and 11.3MHz,respectively.Therefore,the loop band
widths of both PLLs can be incread so that the switching time and the chip area can be reduced.Compared to single-loop
integer-
design with the same loop bandwidth.
Although the input-reference
frequency
of the low-frequency loop is scaled up by 8times;the required frequency range of the oscillator VCO1
in the low-frequency loop is also scaled up from 25to 200MHz.On the other hand,the pha-noi of the ring oscillator is attenuated by the frequency
divider
103dBc/Hz at 600kHz).A novel ring
VCO design that meets all of the tough specifications will be prented in the next ction.
IV .C IRCUIT I MPLEMENTATION
This ction discuss the design consideration and circuit implementation of the major building blocks that are unique and critical to the propod dual-loop synthesizer,namely the two VCOs,the frequency dividers,the charge pump,and the loop filters.Detailed analysis and design of other building blocks will not be prented,either becau they can be found somewhere el or they are too obvious.A.Ring Oscillator VCO1
The schematic of the propod two-stage ring oscillator and its delay cell to meet the required specification as described in Section III are shown in Fig.5(a)and (b),respectively.The delay cell consists of nMOS
transistors
for maintaining oscilla-tion,diode-connected pMOS
transistors
for frequency tuning.The source nodes of
transistors
.
When control
voltage
V ,
transistors
are
Fig.5.Circuit implementation of the ring oscillator VCO1.(a)Ring oscillator.(b)Delay cell.(c)Half circuit of delay cell.
turned
大学体验英语2
klein
off
is proportional
to
.
Bad on the approximate impul-stimulus function(ISF)
and the analysis prented in[8],the pha noi of the oscil-
lator is estimated to be approximately
111.7dBc/Hz at600kHz.
B.LC Oscillator VCO2
As the far-offt pha noi is dominated by the VCO2,an
LC oscillator is adopted to meet the stringent pha-noi speci-
fication.Fig.6shows the schematic of the LC oscillator.Cross-
coupled
transistors
diffusion on the n-well are ud for frequency-tuning pur-
po.The common-mode output voltage is designed at1.1V
to enhance the driving of the frequency
divider
are ud as the current source.
To design an LC oscillator which satisfies the pha-noi re-
quirement with minimum power consumption,inductors with
large inductance and small ries resistance are desired.There-
fore,two-layer inductors are adopted[10]for which the induc-
tance and the quality factor can be scaled up by4and2times,
respectively.For the same reason,pn-junction varactors are in-
terdigitized with
p
is designed so that it does not
overcompen-
Fig.6.Circuit implementation of the LC oscillator VCO2.
sate the LC tank too much(only twice)to reduce pha-noi
contribution by
transistors
124.0dBc/Hz at600-kHz
frequency offt,which agrees well with the simulation using强壮的英文
SpectreRF.
C.Frequency
Dividers
Fig.7.Circuit implementation of the pudo-nMOS divide-by-2frequency
divider.
Fig.8.Block diagram of the programmable-frequency divider
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E.Charge Pumps and Loop Filters
Fig.10shows the circuit implementation of the charge pumps ud in the two loops.Each charge pump consists of two cascode-current sources for both the pull-up and pull-down currents,four complementary switches,and a unity-gain amplifier.By using high-swing cascode current sources,the output impedance is incread for effective current injection.Minimum-size complementary switches are adopted to mini-mize clock feedthrough and charge injection of the switches.The unity-gain amplifier keeps the voltages of nodes VCO
and to be equal so that charge sharing between nodes
VCO,,
谷歌英汉在线翻译
and to output
aboveall
眉毛的画法
急切地
pha
is the pha-detector
gain,
is the VCO gain,
and
