Power Supply Requirements
Table7 shows the minimum current, in addition to I CCQ, that is required by Zynq-7000 devices for proper power-on and configuration. If the current minimums shown in Table6 and Table7 are met, the device powers on after all five supplies have pasd through their power-on ret threshold voltages. The Zynq-7000 device must not be configured until after V CCINT is applied. Once initialized and configured, u the Xilinx Power Estimator (XPE) spreadsheet tool (download at
to estimate current drain on the supplies.
Table 7:Power-On Current for Zynq-7000 Devices
Device I CCPINTMIN I CCPAUXMIN I CCDDRMIN I CCINTMIN I CCAUXMIN I CCOMIN I CCAUX_IOMIN I CCBRAMMIN Units
XC7Z030I CCPINTQ+
70mA
I CCPAUXQ+
40mA
I CCDDRQ+
130mA
per bank
I CCINTQ+
900mA
I CCAUXQ+
60mA
I CCOQ+
90mA
per bank
I CCOAUXIOQ+
40mA
per bank
I CCBRAMQ+
90mA
mA
XC7Z035I CCPINTQ+
70mA
I CCPAUXQ+
40mA
I CCDDRQ+
130mA
per bank
I CCINTQ+
1400mA
I CCAUXQ+
60mA
I CCOQ+
90mA
per bank
I CCOAUXIOQ+
40mA
per bank
I CCBRAMQ+
90mA
mA
XC7Z045I CCPINTQ+
70mA
I CCPAUXQ+
40mA
I CCDDRQ+
130mA
per bank
I CCINTQ+
1400mA
I CCAUXQ+
60mA
I CCOQ+
90mA
per bank
I CCOAUXIOQ+
40mA
per bank
paraI CCBRAMQ+
90mA
mA
XC7Z100I CCPINTQ+
70mA
I CCPAUXQ+
40mA
I CCDDRQ+
130mA
per bank
I CCINTQ+
网上打字赚钱网站
2200mA
I CCAUXQ+
60mA
敬爱的拼音
I CCOQ+
90mA
per bank
I CCOAUXIOQ+
40mA
per bank
I CCBRAMQ+
90mA
mA
XA7Z030I CCPINTQ+
70mA
I CCPAUXQ+
40mA
I CCDDRQ+
130mA
per bank
I CCINTQ+
900mA
I CCAUXQ+
60mA
I CCOQ+
90mA
per bank
I CCOAUXIOQ+
40mA
per bank
I CCBRAMQ+
90mA
mA
XQ7Z030I CCPINTQ+
70mA
I CCPAUXQ+
40mA
I CCDDRQ+
130mA
per bank
I CCINTQ+
900mA
I CCAUXQ+
60mA
I CCOQ+
90mA
per bank
忍耐的意思I CCOAUXIOQ+
40mA
per bank
I CCBRAMQ+
90mA
mA
XQ7Z045I CCPINTQ+
70mA
I CCPAUXQ+
40mA
I CCDDRQ+
130mA
per bank
I CCINTQ+
1400mA
I CCAUXQ+
60mA
I CCOQ+
90mA
per bank
I CCOAUXIOQ+
40mA
per bank
I CCBRAMQ+
90mA
mA
浙大面试
XQ7Z100I CCPINTQ+
70mA
I CCPAUXQ+
40mA
I CCDDRQ+
130mA
per bank
I CCINTQ+
2200mA
I CCAUXQ+
60mA
I CCOQ+
bubbly
90mA
per bank
I CCOAUXIOQ+
40mA
per bank
I CCBRAMQ+
90mA
mA
Table 8:Power Supply Ramp Time
Symbol Description Conditions Min Max Units T VCCPINT Ramp time from GND to 90% of V CCPINT0.250ms T VCCPAUX Ramp time from GND to 90% of V CCPAUX0.250ms T VCCO_DDR Ramp time from GND to 90% of V CCO_DDR0.250ms T VCCO_MIO Ramp time from GND to 90% of V CCO_MIO0.250ms T VCCINT Ramp time from GND to 90% of V CCINT0.250ms T VCCO Ramp time from GND to 90% of V CCO0.250ms T VCCAUX Ramp time from GND to 90% of V CCAUX0.250ms T VCCAUX_IO Ramp time from GND to 90% of V CCAUX_IO0.250ms T VCCBRAM Ramp time from GND to 90% of V CCBRAM0.250ms
T VCCO2VCCAUX Allowed time per power cycle for V CCO–V CCAUX> 2.625V
and V CCO_MIO–V CCPAUX>2.625V
T J = 125°C(1)–300ms
T J = 100°C(1)–500ms
T J = 85°C(1)–800ms
T MGTAVCC Ramp time from GND to 90% of V MGTAVCC0.250ms T MGTAVTT Ramp time from GND to 90% of V MGTAVTT0.250ms
T MGTVCCAUX
Ramp time from GND to 90% of V MGTVCCAUX
0.2
50
ms
Bank I/O Standard V IL
V IH
V OL
V OH I OL I OH V, Min V, Max V, Min V, Max
V, Max V, Min mA mA MIO LVCMOS18–0.30035% V CCO_MIO 65% V CCO_MIO V CCO_MIO +0.300
0.450V CCO_MIO –0.4508–8MIO LVCMOS25–0.3000.700 1.700V CCO_MIO +0.300
0.400V CCO_MIO –0.4008–8MIO LVCMOS33–0.300
0.800
2.000
3.450
0.400V CCO_MIO –0.4008–8MIO
HSTL_I_18
–0.300V PREF –0.100V PREF +0.100V CCO_MIO +0.300
0.400
V CCO_MIO –0.400
8–8DDR SSTL18_I –0.300V PREF –0.125V PREF +0.125V CCO_DDR +0.300V CCO_DDR /2–0.470V CCO_DDR /2+0.470
8
–8
DDR SSTL15–0.300V PREF –0.100V PREF +0.100V CCO_DDR +0.300V CCO_DDR /2–0.175V CCO_DDR /2+0.17513.0–13.0DDR SSTL135–0.300V PREF –0.090V PREF +0.090V CCO_DDR +0.300V CCO_DDR /2–0.150V CCO_DDR /2+0.15013.0–13.0DDR HSUL_12
–0.300V PREF –0.130V PREF +0.130V CCO_DDR +0.300
20% V CCO_DDR
80% V CCO_DDR
0.1
–0.1
Table 8:Power Supply Ramp Time (Cont’d)
egger
Symbol Description
Conditions Min Max Units
PL I/O Levels
Table 11:SelectIO DC Input and Output Levels(1)(2)
I/O Standard
V IL V IH V OL V OH I OL I OH V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I–0.300V REF–0.100V REF+0.100V CCO+0.3000.400V CCO–0.4008–8 HSTL_I_12–0.300V REF–0.080V REF+0.080V CCO+0.30025%V CCO75%V CCO 6.3–6.3 HSTL_I_18–0.300V REF–0.100V REF+0.100V CCO+0.3000.400V CCO–0.4008–8 HSTL_II–0.300V REF–0.100V REF+0.100V CCO+0.3000.400V CCO–0.40016–16 HSTL_II_18–0.300V REF–0.100V REF+0.100V CCO+0.3000.400V CCO–0.40016–16 HSUL_12–0.300V REF–0.130V REF+0.130V CCO+0.30020%V CCO80%V CCO0.1–0.1 LVCMOS12–0.30035% V CCO65% V CCO V CCO+0.3000.400V CCO–0.400Note3Note3 LVCMOS15,
LVDCI_15
–0.30035% V CCO65% V CCO V CCO+0.30025%V CCO75%V CCO Note4Note4
LVCMOS18,
LVDCI_18
–0.30035% V CCO65% V CCO V CCO+0.3000.450V CCO–0.450Note5Note5 LVCMOS25–0.3000.700 1.700V CCO+0.3000.400V CCO–0.400Note6Note6 LVCMOS33–0.3000.800 2.000 3.4500.400V CCO–0.400Note6Note6 LVTTL–0.3000.800 2.000 3.4500.400 2.400Note7Note7 MO
BILE_DDR–0.30020% V CCO80% V CCO V CCO+0.30010%V CCO90%V CCO0.1–0.1 PCI33_3–0.40030% V CCO50% V CCO V CCO+0.50010%V CCO90%V CCO 1.5–0.5 SSTL12–0.300V REF–0.100V REF+0.100V CCO+0.300V CCO/2–0.150V CCO/2+0.15014.25–14.25 SSTL135–0.300V REF–0.090V REF+0.090V CCO+0.300V CCO/2–0.150V CCO/2+0.15013.0–13.0 SSTL135_R–0.300V REF–0.090V REF+0.090V CCO+0.300V CCO/2–0.150V CCO/2+0.1508.9–8.9 SSTL15–0.300V REF–0.100V REF+0.100V CCO+0.300V CCO/2–0.175V CCO/2+0.17513.0–13.0 SSTL15_R–0.300V REF–0.100V REF+0.100V CCO+0.300V CCO/2–0.175V CCO/2+0.1758.9–8.9 SSTL18_I–0.300V REF–0.125V REF+0.125V CCO+0.300V CCO/2–0.470V CCO/2+0.4708–8 SSTL18_II–0.300V REF–0.125V REF+0.125V CCO+0.300V CCO/2–0.600V CCO/2+0.60013.4–13.4 Notes:
1.Tested according to relevant specifications.
snicker2. 3.3V and 2.5V standards are only supported in HR I/O banks.
3.Supported drive strengths of 2, 4, 6, or 8mA in HP I/O banks and 4, 8, or 12mA in HR I/O banks.
4.Supported drive strengths of 2, 4, 6, 8, 12, or 16mA in HP I/O banks and 4, 8, 12, or 16mA in HR I/O banks.
5.Supported drive strengths of 2, 4, 6, 8, 12, or 16mA in HP I/O banks and 4, 8, 12, 16, or 24mA in HR I/O banks.
6.Supported drive strengths of 4, 8, 12, or 16mA
7.Supported drive strengths of 4, 8, 12, 16, or 24mA
8.For detailed interface specific DC voltage levels, e the 7Series FPGAs SelectIO Resources Ur Guide (UG471).
TMDS_33
TMDS_33
3–0.125
3+0.125肯德基帅哥
0(6)
–
Figure 18:Single-Ended Test Setup
Description
I /O Standard Attribute V L
哈迪森
(1)(2)
V H (1)(2)V MEAS
(1)(4)(6)
V REF
(1)(3)(5)
