Application Note:海文考研网
HFAN-2.5.0
Rev 0; 05/04
Single-Ended vs. Differential Methods of Driving a Lar Diode
MAXIM High-Frequency/Fiber Communications Group
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3hfan250.doc 05/25/2004
Single-Ended vs. Differential Methods of Driving a Lar Diode
1 Introduction
A proper interface circuit to connect a driver to a lar diode is esntial for an optimized optical transmitter design. In general, the single-ended drive of lar diodes provides a straight forward solution that requires less components and board space. Drawbacks include a comparatively slow o
utput edge-speed and noi added to the transceiver power supply, which will eventually affect the receiver nsitivity. Recent industrial practice has shown that optical transmitters bad on differential drives are able to overcome the disadvantages associated with a single-ended drive. The purpo of this application note is to reveal how a differential drive provides a faster edge-speed than a single-ended drive.
Lar Driver CP2瓦砾的意思
OUTCP1 OUT+ RD VCC
BIAS RF CF
Figure 1. Single-ended Method of Driving a Lar Diode
VCC
2 Circuit Configuration for Single-Ended Drive and Differential Drive
For a single-ended drive, the lar modulation current is applied either to the lar anode (commoncathode lar) or to the lar cathode (commonanode lar). Figure 1 is a simplified schem
atic for driving a common-anode lar. The modulation current is delivered to the lar cathode through a damping resistor (RD). The lar anode is directly connected to the power supply, and the lar bias is provided from a driver bias output isolated by a ferrite bead. For a balanced DC and AC loading, the driver complementary output is pulled up to Vcc by a parallel network consisting of a ferrite bead and a resistor that matches the equivalence of the lar load and the damping resistor. The RC shunt network (RF and CF) provides high-frequency damping. Capacitance CP (CP1 and CP2) at the driver outputs reprents a combination of output transistor equivalent capacitance, packaging and board layout parasitic capacitances.
Lar Driver CP2
OUTCP1 OUT+ RD
BIAS
Figure 2. Differential Method of Driving a Lar Diode Figure 2 shows one example of a differential drive. The lar cathode is AC-coupled to the driver output via a damping resistor (RD). The driver output is pulled up to Vcc through a ferrite bead to provide a DC bias to the output transistor. The shared node of the driver complementary output and the lar diode anode is connected to Vcc thro
ugh a ferrite bead which provides high-frequency isolation from Vcc. The lar bias is provided in a similar way as in a single-ended drive configuration. Using the same lar diode and driver, a 2.5Gbps optical transmitter bad on differential drive shows more than 20ps improvement in edge-speed than a single-ended drive [1].
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Application Note HFAN-02.5.0 (Rev. 0, 05/04)
3 Charge and Discharge for Single-Ended Drive
The circuit for the single-ended drive in Figure 1 is reorganized in Figure 3. For simplicity, the RF and CF compensation network is ignored in the following discussion. During the lar turn-on period, the output transistor T1 provides a sink current to modulate the lar through the damping resistor RD, and to charge the parasitic capacitor CP1. The full modulation current is only switched to a lar after the CP1 charging is completed. Therefore, the transient current that charges this capacitor is primarily responsible for a degraded rising edgespeed. When the lar is turned off, T1 stops sinking current and the parasitic capacitor CP1 is discharged through a ries network consisting of the lar diode and the damping resistor. This transient current will slow down the lar-off transition, res
ulting in a slow tail in optical output. The charge and discharge loop time constant τSE is estimated as:
CP2pigeons
VCC
CP1
A RD T2 T1
Modulation
Bias
τ SE ≈ ( RD + RL ) ⋅ C P
where RL is the lar equivalent resistance. The contribution of lar ries inductance is ignored in this analysis. The ries resistor RD is necessary to damp the lar overshoot and ringing caud by lar and asmbly inductance. Therefore, reducing the equivalent capacitance at the driver output
node is the key factor for achieving a fast optical edge-speed. Figure 4 prents the simulation results of step respon. The lar diode is modeled as a 5Ω resistor in parallel with a 1pF capacitor. The damping resistor RD is chon as 10Ω. The edge-speed (20%-80%) of the transistors (T1 and T2) ud in this test is approximately 25ps. The simulated edge-speed of lar diode output is listed in Table 1. The falling edge is slower than the rising edge. Table 1. Edge-speed (in ps) and Output Capacitance for a Single-Ended Drive CP (CP1 & CP2) tr/tf (20%-80%) tr/tf (10%-90%) 1pF 41/46 60/72 2pF 53/59 83/97 3pF 71/78 118/125
CP2
VCC
CP1
A RD T2 T1
Modulation
Bias
Figure 3. Charge (top) and Discharge (bottom) Loops for a Single-Ended Drive Circuit. (Dotted lines reprent a transient current for capacitor charge or discharge)
Application Note HFAN-02.5.0 (Rev. 0, 05/04)
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0.055 0.053 0.050 0.048 0.045 0.043 0.040 0.038 0.035 0.033 0.030 0.028 0.025 0.023 0.020 0 100 200 300
1pF 2pF 3pF
400 Time (ps)
500
600
700
800
snb
ashworth
Figure 4. Step Respon Simulation for Single-ended Drive Another disadvantage is that a single-ended drive generates a large transient current flow on the Vcc plane. The transceiver layout and power supply decoupling has to be well designed, otherwi the receiver will pick up noi from the power supply, which eventually may affect the optical receiver nsitivity.
4 Charge and Discharge for Differential Drive
Figure 5 illustrates the current flow for driving a lar diode differentially. When the lar is turned on, the output transistor T1 provides a sink current to charge the parasitic capacitor CP1 at the collector of T1, and to modulate the lar through the damping resistor RD and an AC-coupling capacitor. Since the ferrite beads will force a constant current flow, iCP1 = iCP2. The charge and discharge process is reverd in a similar loop when the driver current is switched to the complementary side during the laroff period. To achieve the same lar modulation current with a differential drive as single-ended drive, the amplitude of the voltage swing over the lar diode and damping resistor should remain the same. This means that the voltage swing at Node A (∆VA) for singled-ended drive should equal (VA-VB) for the differential drive. Therefore, the voltage swing over the parasitic capacitors CP1 and CP2 for the differential drive is only half of that for a single-ended drive. The overall effect is that the differential drive leads to a faster signal transmission. The time constant τDF
for lar-on and lar-off is estimated as:
Figure 5. Charge (top) and Discharge (bottom) Loops for a Differential Driving Circuit. (Dotted lines reprent a transient current for capacitor charge and discharge. Current through the ferrite bead is assumed constant) The time constant τDF for differential drive is about half of the time constant τSE for a single-ended drive, meaning a fast transmitter edge-speed. The
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τ DF ≈ (R D + RL ) ⋅
CP2 1 = ( RD + RL ) ⋅ C P 1 + C P 2 / C P1 2
Application Note HFAN-02.5.0 (Rev. 0, 05/04)
simulation results of step respon are shown in Figure 6 and Table 2. For a 2pF output capacitance the falling edge-speed at 20%-80% and at 10%-90% is improved by 20ps and 43ps respectively. Table 2. Edge-speed (in ps) and Output Capacitance for Differential Drive CP (CP1 & CP2) tr/tf (20%-80%) tr/tf (10%-90%)
0.0425 0.04 0.0375 0.035 0.0325 0.03 0.0275 0.025 0.0225 0.02 0.0175 0.015 0.0125 0.01 0.0075
5 Conclusion
This application note shows that the edge-speed of an optical transmitter can be improved by using a differential lar driver configuration. One of the primary benefits of the differential drive is that it can tolerate more capacitance at the output node. This does not mean, however, that output capacitance can be neglected – good high-frequency board layout techniques and other methods of lowering the output capacitance remain important. Also, in real applications, a number of additional factors (not addresd in this application note) must be considered, including: (a) the lar equivalent capacitance that will introduce another pole into the circuit and (b) the lar electrical-to-optical conversion that will slow the edge speeds and cau asymmetry between the rising and falling edges. Becau of the factors, high-speed operation will require a relatively fast lar diode along with minimization of the lar package inductance.
1pF 34/34 51/50
thor2pF 39/39 58/57
3pF 45/45 71/69
1p 2p 3p
0
100
200
rego300
400 Time (ps)
500
600
新年快乐 韩语700
800
Reference
[1] Application Note: “MAX3735A Output Configuration Part 3: Differential Drive. ” - HFDN26.2 Maxim Integrated Products, November 2003.
Figure 6. Step Respon Simulation for Differential Drive Becau of its symmetrical nature, the differential drive method shows better immunity to capacitive load. The edge-speed degradation from output capacitance is much less than that of a single-ended drive. It also provides a matched ri and fall time, that makes it easy to optimize the transmitter optical eye-diagram. On the other hand, the lar charge and discharge loops include the same external circuit, so it can tolerate more variation and mismatching in board layout, without adding additional noi to the Vcc plane. The disadvantage is that the differential drive approach is bad on AC coupling between the driver and the lar diode, which may result in a low-frequency cutoff problem for some applications.
Application Note HFAN-02.5.0 (Rev. 0, 05/04)
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