专利名称：Bit line gmenting in random access
memories
发明人：David SuitWai Ma,Aiqin Chen
申请号：US10269005
gotye申请日：20021010
我向往的地方公开号：US20040073745A1
公开日：
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20040415
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mono
relationship
专利附图：
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摘要：An integrated memory circuit and corresponding method for gmenting bit lines are provided, where the integrated memory circuit includes a n amplifier, a layered bit line in signal communication with the n amplifier, veral gment pass
transistors in signal communication with the layered bit line, veral gmented bit lines, each in signal communication with a corresponding one of the veral gment pass transistors, respectively, veral memory cell pass transistors in signal communication with one of the veral gmented bit lines, and a plurality of memory cell capacitors, each in signal communication with a corresponding one of the plurality of memory cell transistors, respectively; and where the corresponding method for gmenting bit lines includes receiving a memory cell address, activating a memory cell pass transistor with a wordline corresponding to the memory cell address, receiving a signal indicative of the memory cell charge level on a gmented bit line through the memory cell transistor, activating a gment pass transistor corresponding to the memory cell address, receiving a signal indicative of the memory cell charge level on a layered bit line through the gment pass transistor, and receiving a signal indicative of the memory cell charge level at the n amplifier through the layered bit line.
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申请人：INFINEON TECHNOLOGIES NORTH AMERICA CORP.
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