LMX2364
2.6GHz PLLatinum Fractional RF Frequency Synthesizer with 850MHz Integer IF Frequency Synthesizer
General Description
The LMX2364integrates a high performance 2.6GHz frac-tional frequency synthesizer with a 850MHz low power Integer-N frequency synthesizer.Designed for u in a local oscillator subsystem of a radio transceiver,the LMX2364generates very stable,low noi control signals for UHF and VHF voltage controlled oscillators.It is fabricated using Na-tional’s high performance BiCMOS process.
The RF Synthesizer supports both fractional and integer modes.The N counter contains a lectable,quadruple modulus prescaler and can support fractional denominators from 1to 128.A flexible,4level programmable charge pump supplies output current magnitudes ranging from 1mA to 16mA.Only a single word write is required to power up and tune the synthesizer to a new frequency.
High performance FastLock ™technology makes the LMX2364an excellent choice for applications requiring ag-gressive lock time while maintaining excellent pha noi and spurious performance.The combination of the improved FastLock circuitry,the enhanced fractional compensation engine,and the programmable charge pump architecture gives the designer maximum freedom to optimize the perfor-mance of the synthesizer for the target application.Inte-grated timeout counters greatly simplify the programming aspects of FastLock.The timeout counters reduce the demands on the microcontroller by automatically dingag-ing FastLock after a perscribed number of reference cycles of the pha detector.
The IF synthesizer includes a fixed 8/9dual modulus pres-caler,a two level programmable charge pump,and dedi-cated FastLock circuitry with an integrated timeout counter.The LMX2364offers many performance enhancements over the LMX2354.Improvements in the fractional compensation make the spurs on the LMX2364approximately 6dB better in a typical application.The higher and more flexi
ble frac-tional modulus combined with the higher charge pump cur-rents result in pha noi improvements on the order of 10dB.The cycle slip reduction circuitry of the LMX2364is both easy to u and effective in reducing cycle slipping and allows one to u very high pha detector frequencies without degrading lock times.
Serial data is transferred to the device via a three-wire interface (DATA,LE,CLK).The low voltage logic interface
allows direct connection to 1.8Volt and 3.0Volt devices.Supply voltages from 2.7V to 5.5V are supported.Indepen-dent charge pump supplies for each synthesizer allows the designer to optimize the bias level for the lected VCO.The LMX2364consumes 5.0mA (typical)of current in integer mode and 7.2mA (typical)in fractional mode.The LMX2364is available in a 24Pin Ultra Thin CSP package and 24Pin TSSOP Package.
Features
n RF Synthesizer supports both Fractional and Integer Operating Modes
n Pin Compatible upgrade for LMX2354n 2.7V to 5.5V operation
n Pin and programmable power down
n Fractional N divider supports fractional denominators ranging from 1through 128
n Supports Integer Mode Operation
n Programmable charge pump current levels RF:4level,1–16mA IF:2level,100/800uA
n FastLock Technology with integrated timeout counters n Digital filtered &analog lock detect output n FastLock Glitch Reduction Technology
n Enhanced Low Noi Fractional Compensation Engine n Low voltage programming interface allows direct connection to 1.8V logic
Applications
n Digital Cellular n GPRS n IS-136n GAIT n PDC n EDGE n CDMA
n Zero blind slot TDMA systems n
Cable TV Tuners (CATV)
迪士尼经典动画片FastLock ™is a trademark of National Semiconductor Corporation.
TRI-STATE ®is a registered trademark of National Semiconductor Corporation.
July 2003
LMX23642.6GHz PLLatinum Fractional RF Frequency Synthesizer with 850MHz Integer-N IF Frequency Synthesizer
白话翻译©2003National Semiconductor Corporation
Functional Block Diagram
20050601
Connection Diagrams
24-Pin TSSOP (TM)Package
Ultra Thin 24-Pin CSP (SLE)Package
20050602
ntr是什么意思的缩写20050622
L M X 2364
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LMX2364 Pin Descriptions
Pin Number
Pin Description
TSSOP SLE
21VccRF RF PLL power supply voltage input.Must be equal to V VccIF.May range from2.7V to
5.5V.Bypass capacitors should be placed as clo as possible to this pin and be
connected directly to the ground plane.
方案英文
32VcpRF Power supply for RF charge pump.Must be≥V VccRF and V VccIF.
43CPoutRF RF charge pump output.
54GND Ground for RF PLL digital circuitry.
65FinRF RF prescaler input.Small signal input from the VCO.
76FinRF*RF prescaler complementary input.For single-ended operation,a bypass capacitor
should be placed as clo as possible to this pin and be connected directly to the
ground plane.
87GND Ground for RF PLL analog circuitry.
98OSCinRF RF R counter input.Has a V CC/2input threshold when configured as an input and can
be driven from an external CMOS or TTL logic gate.
长脸男生适合的发型
109OSCinIF Oscillator input which can be configured to drive both the IF and RF R counter inputs
or only the IF R counter depending on the state of the OSC programming bit.
1110Ftest/LD Programmable multiplexed output pin.Can function as general purpo CMOS
TRI-STATE®I/O,analog lock detect output,digital filtered lock detect output,or N&R
divider output.
1211ENRF RF PLL Enable.Powers down RF N and R counters,prescaler,and TRI-STATE
charge pump output when LOW,regardless of the state RF_PD bit.Bringing ENRF
high powers up RF PLL depending on the state of RF_PD control bit.
1312ENIF IF PLL Enable.Powers down IF N and R counters,prescaler,and will TRI-STATE the
charge pump output when LOW,regardless of the state IF_PD bit.Bringing ENIF high
powers up IF PLL depending on the state of IF_PD control bit.
1413CLK High impedance CMOS Clock input.Data for the control registers is clocked into the
24-bit shift register on the rising edge.
1514DATA Binary rial data input.Data entered MSB first.The last three bits are the control
bits.High impedance CMOS input.
1615LE Latch enable.High impedance CMOS input.Data stored in the shift register is loaded
into one of the7internal latches when LE goes HIGH.
1716GND Ground for IF analog circuitry.
1817FinIF*IF prescaler complementary input.For single-ended operation,a bypass capacitor
should be placed as clo as possible to this pin and be connected directly to the
ground.
1918FinIF IF prescaler input.Small signal input from the VCO.
2019GND Ground for IF digital circuitry.
2120CPoutIF IF charge pump output.
2221VcpIF Power supply for IF charge pump.Must be≥V VccRF and V VccIF.
2322VccIF IF power supply voltage input.Must be equal to V VccRF.Input may range from2.7V to
5.5V.Bypass capacitors should be placed as clo as possible to this pin and be
connected directly to the ground plane.
2423FLoutIF IF FastLock Output.Also functions as Programmable TRI-STATE CMOS output.
124FLoutRF RF FastLock Output.Also functions as Programmable TRI-STATE CMOS output.
3
Absolute Maximum Ratings
(Notes 1,2)Parameter
Symbol Value
Units Min Typ
Max Power Supply Voltage
V Vcc −0.3 6.5V V Vcp −0.3 6.5V Voltage on any pin with GND =0V V CC −0.3V CC +0.3V Storage Temperature Range T s −65
+150˚C Lead Temperature (Solder 4c.)
T L
+260
˚C
Recommended Operating Conditions
Parameter
Symbol Value
Units Min Typ
Max Power Supply Voltage
V VccRF 2.7 5.5V V VccIF V VccRF V VccRF V V VcpRF V VccRF 5.5V V VcpIF
V CCIF 5.5V Operating Temperature
T A
−40
+85
˚C
Note 1:“Absolute Maximum Ratings”indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is intended to be functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,e the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.
Note 2:This Device is a high performance RF integrated circuit with an ESD rating <2kV and is ESD nsitive.Handling and asmbly of this device should only be done at ESD-free workstations.
Electrical Characteristics
(V Vcc =V Vcp =3.0V;−40˚C ≤T A ≤+85˚C except as specified)
Symbol Parameter
Conditions
Value
Units
Min
watchman
Typ
Max
I CC PARAMETERS I CC RF
Power Supply Current,RF Synthesizer,Integer Mode V ENIF =V CLK =V DATA =V LE =LOW V ENRFV =HIGH FE =0
5.0
成都化妆6.3mA
Power Supply Current,RF Synthesizer,Fractional Mode
V ENIF =V CLK,=V DATA =V LE =0V V ENRF =HIGH FE =1
7.28.0mA
I CC IF Power Supply Current,IF Synthesizer
V ENRF =V CLK =V DATA =V LE =LOW V ENIF =HIGH
2.4
3.2mA I CC IF PD
Power Down Current
V ENRF =V ENIF =LOW V CLK =V DATA =V LE =LOW 5.0
20
µA
金色雨林RF SYNTHESIZER PARAMETERS f FinRF Operating Frequency Prescaler =8/9/12/135001200MHz Prescaler =16/17/20/2112002600MHz
N
Continuous N Divider Range,Fractional Mode Prescaler =8/9/12/13404095Prescaler =16/17/20/21808191Continuous N Divider Range,Integer Mode
Prescaler =8/9/12/1340266,239Prescaler =16/17/20/21
80532,479R
R Divider Range,Fractional Mode 1511R Divider Range,Integer Mode (Note 3)
1
64,897f COMP Pha Detector Frequency 15MHz p FinRF
RF Input Sensitivity
V CC =3.0V −150dBm V CC =5.0V
−10
dBm L M X 2364
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Electrical Characteristics(V
Vcc
=V Vcp=3.0V;−40˚C≤T A≤+85˚C except as specified)(Continued)
Symbol Parameter Conditions
Value
Units Min Typ Max
RF SYNTHESIZER PARAMETERS
I CPoutRF SRCE RF Charge Pump Source
Current RF_CP=0
V CPoutRF=V VcpRF/2
1mA RF_CP=1
V CPoutRF=V VcpRF/2
4mA RF_CP=2
V CPoutRF=V VcpRF/2
8mA RF_CP=3
h m p公司V CPoutRF=V VcpRF/2
16mA
I CPoutRF SINK RF Charge Pump Sink
Current RF_CP=0
V CPoutRF=V VcpRF/2
−1mA RF_CP=1
V CPoutRF=V VcpRF/2
−4mA RF_CP=2
V CPoutRF=V VcpRF/2
−8mA RF_CP=3
V CPoutRF=V VcpRF/2
−16mA
I CPoutRF TRI RF Charge Pump
TRI-STATE Current 0.5≤V CPoutRF≤V VcpRF−0.5
−10.010.0nA
I CPoutRF%MIS RF CP Sink vs.CP Source
Mismatch V CPoutRF=V VcpRF/2
T A=25˚C
3.5%
I CPoutRF%V RF CP Current vs.CP
Voltage 0.5≤V CPoutRF≤V VcpRF−0.5
T A=25˚C
RF_CP=0,1,or2
510%
I CPoutRF%TEMP RF CP Current vs.
Temperature VP CPoutRF=V VcpRF/2
810%
IF SYNTHESIZER PARAMETERS
f FinIF Operatin
g Frequency50850MHz N IF Continuous N Divider
Range
56262,143
R IF R Divider Range332,767
f COMP Pha Detector Frequency10MHz p FinIF IF Input Sensitivity 2.7≤V Vcc≤5.5V−100dBm
I CPoutIF SRCE IF Charge Pump Source
Current IF_CP=0
V CPoutIF=V VcpIF/2
100µA IF_CP=1
V CPoutIF=V VcpIF/2
800µA
I CPoutIF SINK IF Charge Pump Sink
Current IF_CP=0
V CPoutIF=V VcpIF/2
−100µA IF_CP=1
V CPoutIF=V VcpIF/2
−800µA
I CPout TRI IF Charge Pump
TRI-STATE Current 0.5≤V CPout≤V VcpIF−0.5
−2.0 2.0nA
I CPoutIF%MIS IF CP Sink vs.CP Source
Mismatch V CPoutIF=V VcpIF/2
T A=25˚C
5%
I CPoutIF%V IF CP Current vs.CP
Voltage 0.5≤V CPoutIF≤V VcpIF−0.5
T A=25˚C
510%
I CPoutIF%TEMP IF CP Current vs.
Temperature V CPoutIF=V VcpIF/2
8%
LMX2364
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Electrical Characteristics (V Vcc =V Vcp =3.0V;−40˚C ≤T A ≤+85˚C except as specified)
(Continued)
Symbol
Parameter
Conditions
Value
Units
Min
Typ
Max
OSCILLATOR PARAMETERS f OSC Oscillator Operating Frequency
2110MHz v OSC Oscillator Sensitivity OSCinRF,OSCinIF 0.5
V Vcc V I OSC
Oscillator Input Current
V OSC =V Vcc 100
µA V OSC =0V
−100µA
DIGITAL INTERFACE (DATA,CLK,LE,ENIF,ENRF,Ftest/LD,FLoutRF,FLoutIF)V IH High-Level Input Voltage 2.7≤V Vcc ≤3.2 1.6V 3.2<V Vcc ≤5.5
2
鄙视英文V V IL Low-Level Input Voltage 0.4V I IH High-Level Input Current V IH =V CC −1.0 1.0µA I IL Low-Level Input Current V IL =0−1.0 1.0
µA V OH High-Level Output Voltage I OH =−500µA V CC −0.4
V V OL Low-Level Output Voltage I OL =500µA
0.4
V MICROWIRE INTERFACE TIMING
T CS Data to Clock Set Up Time See Data Input Timing 50ns T CH Data to Clock Hold Time See Data Input Timing 10ns T CWH Clock Pul Width High See Data Input Timing 50ns T CWL Clock Pul Width Low See Data Input Timing 50ns T ES Clock to Load Enable Set Up Time
See Data Input Timing 50ns T EW
Load Enable Pul Width
See Data Input Timing
50ns
PHASE NOISE L F1Hz (f)RF
RF Synthesizer’s
Normalized Pha Noi Contribution,Fractional Mode (Note 4)
RF_OM =1(Fractional Mode)f =3KHz
TCXO Reference Source RF_CP =1(4mA)V ENIF =LOW
−208dBc/Hz
RF Synthesizer’s
Normalized Pha Noi Contribution,Integer Mode (Note 4)
RF_OM =0(Integer Mode)f =3KHz
TCXO Reference Source RF_CP =2(4mA)V ENIF =LOW
−215dBc/Hz
L F1Hz (f)IF
IF Synthesizer’s
Normalized Pha Noi Contribution (Note 4)
f =3KHz
TCXO Reference Source IF_CP =1(800mA)V ENRF =LOW
−212dBc/Hz
Note 3:Some reference divider ratios between the minimum and maximum are not realizable.See th
e ction on R divider programming for more details.Note 4:Normalized Pha Noi Contribution is defined as:L F1Hz (f)=L(f)–20·log(N)–10log(f COMP )where L(f)is defined as the single side band pha noi measured at an offt frequency,f,in a 1Hz Bandwidth.The offt frequency,f,must be chon sufficiently smaller than the PLL’s loop bandwidth,yet large enough to avoid substantial pha noi contribution from the reference source.
L M X 2364
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