DS04–21301–5E
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Copyright
© 1994 by FUJITSU LIMIED
ASSP SERIAL INPUT PLL FREQUENCY SYNTHESIZER如何阅读文章
MB1504/MB1504H/MB1504L
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. How-ever, it is advid that normal precautions be taken to avoid application of any voltage higher than maximum rated volt-ages to this high impedance circuit.
PLASTIC PACKAGE
FPT-16P-M06
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 520MHz PRESCALER
The Fujitsu MB1504/MB1504H/MB1504L, utilizing BI-CMOS technology, is a single chip rial input PLL frequency synthesizer with pul-swallow function.
The MB1504 ries contains a 520MHz two modulus prescaler that can lect either 32/33or 64/65 divide ratio; control signal generator; 16-bit shift register; 15-bit latch;programmable reference divider (binary 14-bit programmable reference counter); 1-bit switch counter; pha comparator with pha inver function; charge pump; crystal oscillator; 19-bit shift register; 18-bit latch; and a programmable divider (binary 7-bit swallow counter and binary 11-bit programmable counter).
The MB1504 operates from a low supply voltage (3V typ) and consumes low power (30mW at 520MHz).
FEATURES
•High operating frequency: f IN MAX =520MHz (V IN MIN =0.20V P-P )•On-chip prescaler
•Low power supply voltage: 2.7V to 5.5V (3.0V typ)
•Low power supply consumption: 30mW (3.0V, 520MHz operation)•Serial input 18-bit programmable divider consisting of:–Binary 7-bit swallow counter (Divide ratio: 0 to 127)艾滋病的英文简称是
–Binary 11-bit programmable counter (Divide ratio: 16 to 2047)•Serial input 15-bit programmable reference divider consisting of:
–Binary 14-bit programmable reference counter (Divide ratio: 8 to 16383)–1-bit switch counter (SW) Sets divide ratio of prescaler • 2 types of pha detector output
–On-chip charge pump (Bipolar type)–Output for external charge pump
•
asscunt
Wide operating temperature: T A =–40_C to +85_C
PLASTIC PACKAGE
DIP-16P-M04best friend什么意思
白木耳什么意思
MB1504MB1504L
MB1504H V P Voltage V OOP Voltage Lock up Time D O Output Width High-level
Output Current
Low-level
Output Current
8V max 10V max 8V max
8.5V max 10.0V max 8.5V max
Middle speed High speed Low speed
Middle Low High
Middle High Lowsurvey
Middle Low High
MB1504 Product Line
MB1504MB1504H MB1504L
MB1504H MB1504/1504L 1234
5678
9
10111213141516OSC IN OSC OUT
V P V CC D O GND LD f in
ØR ØP f P f r FC LE Data Clock
( TOP VIEW )
PIN ASSIGNMENT
ABSOLUTE MAXIMUM RATINGS (e NOTE)
Rating
mtf什么意思啊Power Supply Voltage Symbol Value Unit NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational ctions of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Output Voltage Output Current V CC I OUT mA V PH +10
V V T STG
°C
Storage Temperature –55 to +125
Open-drain Output V V OUT V –0.5 to +7.0V CC to 12.0–0.5 to V CC +0.5Condition V P ,V PL V CC to 10.0V OOPH
–0.5 to 11.0V OOP ,V OOPL MB1504H MB1504/1504L
–0.5 to 9.0
————
MB1504 MB1504H MB1504L
MB1504MB1504H MB1504L
PIN DESCRIPTIONS
receive是什么意思Pin No.
Pin Name Descriptions
12
3OSC IN V P Oscillator input Oscillator output
A crystal is placed between OSC IN and OSC OUT .Power supply input for charge pump 4V CC Power supply voltage input
OSC OUT
D O 5Charge pump output
The pha characteristics can be inverd depending upon the FC input.6
GND
Ground
LD Pha comparator output
This pin outputs high when the pha is locked. While the pha difference of f r and f p exists, the output level goes low.
f IN Prescaler input
The connection with an external VCO should be an AC connection.78
Clock
9Clock input for 19-bit shift register and 16-bit shift register
Each rising edge of the clock shifts one bit of data into the shift registers.
Serial data of binary code input
The last bit of the data is a control bit. The last data bit specifies which latch is activated.When the last bit is high level and LE is high-level, data is transferred to the 15-bit latch.When the last bit is low
level and LE is high level, data is transferred to the 18-bit latch.
10Data 11LE Load enable input (with internal pull up resistor)
When LE is high level (or open), data stored in the shift register is transferred to the latch depending on the control data.
FC Pha lecting input of pha comparator (with internal pull up resistor)
When FC is low level, the charge pump and pha detector characteristics can be inverd.13finish什么意思
Monitor pin of pha comparator input
It is the same as the programmable reference divider output.14f r f P Monitor pin of pha comparator input
It is the same as the programmable divider output.
12Outputs for external charge pump
The pha characteristics can be inverd depending on the FC input.The ØP pin is an N-channel o
pen-drain output.
1516
ØP ØR
I/O I O
——O —
O
I
I
I
I
O
O
O O O
MB1504
MB1504H
MB1504L FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is input using the Data pin, Clock pin and LE pin. The 15-bit programmable reference divider and 18-bit programmable divider are controlled, respectively.
On rising edge of the clock, one bit of the data shifts into the internal shift registers.
When load enable (LE) is high level (or open), data stored in the shift registers is transferred to the 15-bit latch or 18-bit latch depending upon the control bit level.
Control data “H” : Data is transferred into the 15-bit latch.
Control data “L” : Data is transferred into the 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
The programmable reference divider consists of a 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is shown below.
SW: Divide ratio of prescaler tting bit
SW=“H”:32
SW=“L”:64
S1 to S14: Divide ratio of programmable reference counter tting bits (8 to 16383)
C: Control bit (control bit is t to high)
