Boost capacitor for the high-side FET gate driver. Connect 0.01 mF low ESR capacitor from BOOT pin to PH pin
Feedback voltage for the regulator. Connect to output voltage divider.
On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.
Input supply voltage. Bypass VIN pin to GND pin clo to device package with a high quality, low ESR ceramic capacitor.
Source of the high side power MOSFET. Connected to external inductor and diode.
OSCILLATOR
NON-SWITCHING QUIESCENT CURRENT
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SHUTDOWN QUIESCENT CURRENT
INTERNAL SLOW START TIME
升压电容为高侧FET栅极驱动器。从BOOT引脚连接0.01μF的低ESR电容PH引脚
反馈电压调节器。连接到输出电压分压器。
开/关控制。低于0.5 V时，设备停止开关。浮动引脚来启用。
输入电源电压。绕道VIN引脚连接到GND引脚靠近器件封装，具有高品质，低ESR的陶瓷电容。
源高侧功率MOSFET的。连接到外部电感器和二极管。
振荡器
非开关静态电流
关机静态电流
内部慢启动时间
DETAILED DESCRIPTION
Oscillator Frequency
The internal free running oscillator ts the PWM switching frequency at 500 kHz. The 500 kHz switching
frequency allows less output inductance for the same output ripple requirement resulting in a smaller output
inductor
详细说明
振荡器频率
内部自由运行的振荡器设置PWM开关频率为500 kHz。500 kHz的开关
频率允许更小的输出电感为相同的输出纹波要求产生较小的输出
感应器
V oltage Reference The voltage reference system produces a precision reference signal by scaling the output of a temperature stable bandgap circuit. The bandgap and scaling circuits are trimmed
rrcoinduring production testing to an output of 1.221 V at room temperature.
参考电压的电压参考系统通过缩放温度稳定的带隙电路的输出端产生一个精确的参考信号。带隙和缩
放电路中的生产检测到的1.221 V时输出在室温修整。
Enable (ENA) and Internal Slow Start
The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold
voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled
below the threshold voltage, the regulator stops switching and the internal slow start rets. Connecting the pin
to ground or to any voltage less than 0.5 V will disable the regulator and activate the shutdown mode. The
quiescent current of the TPS5450 in shutdown mode is typically 18 μA.
The ENA pin has an internal pullup current source, allowing the ur to float the ENA pin. If an application
requires controlling the ENA pin, u open drain or open collector output logic to interface with the pin. To limit
the start-up inrush current, an internal slow-start circuit is ud to ramp up the reference voltage from 0 V to its
final value, linearly. The internal slow start time is 8 ms typically.
启用（ENA）和内部慢启动
该ENA引脚提供了电气上的调节器的开/关控制。一旦ENA引脚电压超过阈值
电压调节器开始工作，内部慢启动开始上升。如果ENA引脚电压被拉
低于阈值电压时，稳压器停止开关和内部慢启动复位。连接销
到地或以任何电压小于0.5伏将禁用调节器和激活关断模式。该
在关断模式下，TPS5450的静态电流典型值为18μA。
该ENA引脚具有内部上拉电流源，允许用户自由浮动的ENA引脚。如果一个应用程序
需要控制ENA引脚，使用漏极开路或集电极开路输出逻辑与引脚接口。为了限制andida
启动浪涌电流，内部慢启动电路用于从0V到坡道的参考电压的
终值，线性。内部慢启动时间为8毫秒典型。
Undervoltage Lockout (UVLO)香港大学研究生专业
The TPS5450 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input
voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the
internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start
threshold voltage is reached, the internal slow start is relead and device start-up begins. The device operates
until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
Boost Capacitor (BOOT)
Connect a 0.01 μF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
档案的读音values over temperature.
Output Feedback (VSENSE) and Internal Compensation
The output voltage of the regulator is t by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage
reference 1.221 V.
The TPS5450 implements internal compensation to simplify the regulator design. Since the TPS5450 us巨星prince去世
voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover
frequency and a high pha margin for good stability. See the Internal Compensation Network in the applications
ction for more details.
欠压锁定（UVLO）
该TPS5450集成了欠压锁定电路，以保持禁用该设备当VIN（输入
电压）低于UVLO启动电压阈值。在上电时，内部电路保持非活动状态和英语在线学习网站
内部慢启动接地，直到VIN超过UVLO启动阈值电压。一旦UVLO启动
阈值电压为止，在内部启动慢释放，装置启动开始。该器件的工作
直到VIN低于UVLO停止阈值电压。在UVLO比较典型的滞后为330毫伏。
升压电容（引导）
连接之间的BOOT引脚和PH引脚0.01μF的低ESR陶瓷电容器。该电容可提供
栅极驱动电压的高侧MOSFET。X7R或X5R级电介质，由于其稳定的建议
值随温度。
输出反馈（VSENSE）和内部补偿
稳压器的输出电压由反馈的外部电阻分压器的中点电压设定
网络向VSENSE引脚。在稳态操作中，VSENSE引脚电压应该等于电压
参考1.221 V.
该TPS5450实现内部补偿，简化了稳压器设计。由于使用TPS5450
电压模式控制，一个类型3补偿网络被设计在芯片上，以提供高的交叉
频率和高相位裕度为良好的稳定性。看到内部补偿网络中的应用
更多的细节部分。
V oltage Feed Forward
The internal voltage feed forward provides a constant dc power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient respon. Voltage feed forward
varies the peak ramp voltage inverly with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain, i.e
电压前馈
内部电压前馈提供了一个恒定的直流功率级的增益，尽管与输入的任何变化
电压。这极大地简化了稳定性分析和改善瞬态响应。电压前馈
而变化的峰值斜坡电压反比于输入电压，使得调制器和功率级的增益是
在该前馈增益常数，即
Overvoltage Protection
The TPS5450 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from
output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage
and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the h
igh-side
MOSFET will be forced off. When the VSENSE pin voltage drops lower than the threshold, the high-side
MOSFET will be enabled again.
Thermal Shutdown
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The TPS5450 protects itlf from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction
temperature drops 14°C below the thermal shutdown trip point.
PCB Layout
Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN pin, and the TPS5450 ground pin. The best way to do this
is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass
capacitor as clo as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7 μF ceramic
with a X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC, with an expod area for connection
to the PowerPAD. U vias to connect this ground area to any internal ground planes. U additional vias at the
ground side of the input and output filter capacitors as well. The GND pin should be tied to the PCB ground by
connecting it to the ground area under the device as shown below.
The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is
the switching node, the inductor should be located very clo to the PH pin and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed clo to the device to
minimize the output current loop area. Connect the boot capacitor between the pha node and the BOOT pin as
shown. Keep the boot capacitor clo to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by the PH pin, Lout, Cout and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to t the output voltage. Do not
route this trace too clo to the PH trace. Due to the size of the IC package and the device pin-out, the trace
笨蛋的英文
may need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if a
trace under the output capacitor is not desired.
If using the grounding scheme shown in Figure 9, u a via connection to a different layer to route to the ENA
Pin.
过压保护
阿根廷首都英文
该TPS5450具有过压保护（OVP）电路的恢复时，尽量减少电压过冲
输出故障情况。OVP电路包括过压比较器来比较VSENSE引脚电压
和112.5％×VREF的阈值。一旦VSENSE引脚电压大于阈值较高时，高侧
