Implementation
Overview
This chapter provides the information needed to map GTX_DUAL tiles instantiated in a design to device resources, including:•The location of the GTX_DUAL tiles on the available device and package combinations.
•The pad numbers of external signals associated with each GTX_DUAL tile.
•
How GTX_DUAL tiles and clocking resources instantiated in a design are mapped to available locations with a ur constraints file (UCF).
It is a common practice to define the location of GTX transceivers early in the design
process to ensure correct usage of clock resources and to facilitate signal integrity analysis during boar
d design. The implementation flow facilitates this practice through the u of location constraints in the UCF.
While this chapter describes how to instantiate GTX_DUAL clocking components, the details of the different GTX_DUAL tile clocking options are discusd in “Clocking,” page 96.
Ports and Attributes
Table 4-1 shows the external ports associated with each GTX_DUAL tile.Table 4-1:
GTX_DUAL Tile External Ports Port
Dir
Domain
Description
MGTTXP0MGTTXN0MGTTXP1MGTTXN1Out
Embedded TX Clock
Differential transmit data pairs for GTX transceivers 0 and 1
MGTRXP0MGTRXN0MGTRXP1MGTRXN1In
Embedded RX Clock
Differential receive data pairs for GTX transceivers 0 and 1
MGTREFCLKP MGTREFCLKN In N/A Differential reference clock input pair MGTAVCCPLLfc是什么意思啊
Analog
Analog
Pad for 1.0V supply for PLL
Figure 4-8:XC5VTX150T-FF1156 GTX Placement (1 of 6)
Table5-3 shows example ttings for veral standard protocols. Table 5-3:Communication Standards
Standard
Line
Rate
[Gb/s]
TX/RX
USRCLK
Frequency
[MHz]
TX/RX USRCLK2cmcc是什么
Frequency [MHz]Reference
Clock
英文字母26个字母表Frequency
REFCLK
[MHz]
PLL Clock
Frequency
[GHz]
Reference
Clock
Divider
Setting
PLL_DIVSEL
_REF
ε{1,2}
Feedback
Loop Divider
Setting
PLL_DIVSEL
_FB
ε{1,2,3,4,5}
Divider
Settings:
PLL_RXDIVSEL
_OUT_(0/1)(1)
PLL_TXDIVSEL
_OUT_(0/1)(1)
ε{1,2,4} 1-byte Logic
Interface(2,10)
2-byte
Logic
Interface(3)
4-byte
Logic
Interface(4)
INTDATAWIDTH = 1 (20-bit Internal Datapath) →(DIV=5)
FC4 4.25212.5NA212.5106.25212.5 2.125121 FC2 2.125106.25212.5106.2553.125212.5 2.125122 FC1 1.062553.125106.2553.12526.5625212.5 2.125124
XAUI 3.125156.25312.5156.2578.125312.5
1.56251
1
1 156.252
10GBASE-
CX4
3.125156.25312.5156.2578.125312.5 1.5625111
GigE 1.2562.512562.531.25125 2.5144
Aurora 6.25312.5NA312.5156.25156.25 3.125141 3.125156.25312.5156.2578.125156.25 1.5625121 2.512525012562.5250 2.5122 1.2562.512562.531.25250 2.5124
Serial RapidIO 3.125156.25312.5156.2578.125156.25 1.5625121 2.512525012562.5125 2.5142 1.2562.512562.531.25125 2.5144
SATA III 6.0300NA300150150 3.0141 SATA
Generation
2
315030015075150 1.5121
SATAdarma
Generation
1
1.5751507537.5150 1.5122
sarah怎么读英语
PCI
shivaree
Express,
Rev. 2
5.0250NA250125250 2.5121英文短文
PCI
Express,
Rev. 1.0a,
Rev. 1.1
2.512525012562.5100 2.5152 Infiniband 2.512525012562.5125 2.5141
CPRI(5)2.4576122.88245.76122.8861.44122.88 2.4576142 1.228861.44122.8861.4430.72122.88 2.4576144
OBSAI(5)3.072153.6307.2153.676.8153.6 3.072142 1.53676.8153.676.838.4153.6 3.072144
HD-SDI(7) 1.48574.25148.574.2537.125148.5 2.97144 3G-SDI 2.970148.5297.0148.574.25148.5 2.97142
Shared PMA PLL
happenSee “Clocking,” page 96 for details on supplying CLKIN to the shared PMA PLL.Depending on the width of the RX and TX interface to the FPGA logic resources, the following fixed ratios exist between RXUSRCLK and RXUSRCLK2 frequencies and between TXUSRCLK and TXUSRCLK2 frequencies:1.1-byte RX/TX data interface to the fabric: TX/RXUSRCLK2=2x TX/RXUSRCLK 2.2-byte RX/TX data interface to the fabric: TX/RXUSRCLK2=TX/RXUSRCLK 3.
4-byte RX/TX data interface to the fabric: TX/RXUSRCLK2=0.5x TX/RXUSRCLK
“FPGA TX Interface” in Chapter 6 contains details on generating TXUSRCLK and TXUSRCLK2.
“FPGA RX Interface” in Chapter 7 contains details on generating RXUSRCLK and RXUSRCLK2.
INTDATAWIDTH =0 (16-bit Internal Datapath) → (DIV =4)
Interlaken 6.25390.625NA (9)390.625195.3125390.625 3.1251213.125195.3125NA (9)195.31259
7.65625390.625 3.125122OC48 2.488155.5311155.577.75311.04 2.488.32122SFI-5(8) 3.125195.3125390.625195.312597.65625195.313 3.1251422.488155.5311155.577.75155.52 2.48832142SPI-5(8) 2.488155.5311155.577.75155.52 2.48832142TFI-5(8)
3.110419
4.4388.8194.497.2194.4 3.11041422.488
diman155.5
311
155.5
77.75
155.52
2.48832
石家庄英语1
4
2
Notes:
1.
See “Parallel In to Serial Out,” page 149 and “Serial In to Parallel Out,” page 183 for more details about the divider tting.2.1-byte (8/10-bit) ur interface. Set RXDATAWIDTH =TXDATAWIDTH =0, RX/TXUSRCLK2 rate =2x RX/TXUSRCLK rate.3.2-byte (16/20-bit) ur interface. Set RXDATAWIDTH =TXDATAWIDTH =1, RX/TXUSRCLK2 rate =1x RX/TXUSRCLK rate.4.4-byte (32/40-bit) ur interface. Set RXDATAWIDTH =TXDATAWIDTH =2, RX/TXUSRCLK2 rate =0.5x RX/TXUSRCLK rate.5.Synchronous system.
6.This data rate is supported using 5x digital oversampling. Set OVERSAMPLE_MODE =TRUE.
7.Other frequency is 0.1% lower.
8.Maximum data rate.
9.
When using the internal Gearbox, a 1-byte interface is not supported. A 1-byte interface can be implemented by using an external Gearbox in the FPGA logic.
10.A 1-byte interface is NOT supported with data rates of 4.25Gb/s or higher.
Table 5-3:Communication Standards (Cont’d)
Standard
Line
Rate
[Gb/s]
TX/RX
USRCLK
Frequency [MHz]TX/RX USRCLK2
Frequency [MHz]
Reference Clock Frequency REFCLK [MHz]PLL Clock Frequency [GHz]Reference Clock Divider Setting PLL_DIVSEL
_REF
ε{1,2}
Feedback
Loop Divider
Setting
PLL_DIVSEL
_FB
ε{1,2,3,4,5}
Divider
Settings:
PLL_RXDIVSEL
_OUT_(0/1)(1)
PLL_TXDIVSEL _OUT_(0/1)(1) ε{1,2,4}1-byte Logic
Interface (2,10)
2-byte Logic Interface (3)4-byte Logic
Interface (4)
