Multi-modulus divider retiming circuit

更新时间:2023-07-13 12:57:22 阅读: 评论:0

sleepwalk专利名称:Multi-modulus divider retiming circuit
发明人:Chiewcharn Narathong,Wenjun Su
confluence
申请号:US11560678
申请日:20061116e business
四级答案公开号:US07924069B2criminal charge
5分钟公开日:
利物浦大学官网20110412
专利内容由知识产权出版社提供
专利附图:
摘要:A multi-modulus divider (MMD) receives an MMD input signal and outputs an MMD output signal SOUT. The MMD includes a chain of modulus divider stages (MDSs).Each MDS receives an input signal, divides it by either two or three, and outputs the result as an output signal. Each MDS responds to its own modulus control signal that controls
whether it divides by two or three. In one example, a quential logic element outputs SOUT. The low jitter modulus control signal of one of the first MDS stages of the chain is ud to place a quential logic element into a first state. The output signal of one of the MDS stages in the middle of the chain is ud to place the quential logic element into a cond state. Power consumption is low becau the quential logic element is not clocked at the high frequency of the MMD input signal.
2013广东高考作文题目申请人:Chiewcharn Narathong,Wenjun Su
成长的烦恼高清下载地址:Laguna Niguel CA US,San Diego CA US
nih
国籍:US,US
代理人:Jiayu Xu
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