专利名称：Cache unit capable of efficiently insuring
katebeckinsalecache coherence
bbc在线收听发明人：Nishida, Masato c/o NEC Corporation,Hinata,
Norio c/o NEC Koufu, Ltd.
金山在线快译申请号：EP89118583.7
香妃鸡
southampton申请日：19891006
公开号：EP0363840A3
公开日：半轴油封>intouchable>qq名字英文
19910911
专利内容由知识产权出版社提供
专利附图：
摘要：In a multiprocessor system including a plurality of cache units which are
connected in common to a main storage (20) and to instruction processing units,
respectively, each cache unit (3n) compris a flag circuit (5n) divided into a plurality of flag bit areas (FA-1 to FA-M) which correspond to block areas (BA-1 to BA-M) of a cache memory (4n). Each flag bit area memorizes a flag bit corresponding to a block memorized in the corresponding block area to indicate prence or abnce of one of memory blocks in a common memory area of the main storage in correspondence to the memorized block. Supplied with a cache clear request (CRn) from an n-th one (1n) of the instruction processing units, a cache clear circuit (6n) clears the cache memory so as to era the memorized block when the flag bit indicates prence of the above-mentioned one of the memory blocks in the common memory area. When a block fetching circuit (7n) stores a memory block fetched from the main storage in the cache memory, a fetch detecting circuit (8n) detects whether the fetched memory block is prent or abnt in the common memory area. When the fetched memory block is prent in the common memory area, a flag tting circuit (9n) ts the flag bit indicative of prence in the corresponding flag bit area.
申请人：NEC CORPORATION
地址：7-1, Shiba 5-chome Minato-ku Tokyo JP
rter国籍：JP
flanker
代理机构：VOSSIUS & PARTNER
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