Designing SAR ADC Drive Circuitry
by Rick Downs, Applications Engineering Manager and Miro Oljaca, Systems Engineer Data Acquisition Products, Texas Instruments, Incorporated
Part I: A Detailed Look at SAR ADC Operation
Designing buffer circuitry for driving successive-approximation (SAR) ADCs requires knowledge of the load that the inputs prent. Specifications in data sheets may mislead the ur into thinking that analog inputs, for example, are static when in fact they are a very dynamic load. This three-part article will look at the architecture of modern SAR ADCs, and examine the conversion process in detail. In this first part the operation of a modern SAR ADC is discusd. A detailed, step-by-step analysis is then given, illustrating the sampling and conversion process. The final part discuss charge distribution during the sampling process. This analysis will give the ur of the deviceship pop
a better understanding of the inner operations of a charge-redistribution ADC.
1. The SAR ADC Structure
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Fig. 1: Reprentative SAR Input Stage
Fig. 1 shows a reprentative three bits of a typical SAR ADC (the ADS8361). Looking at this example, we will examine a three-bit conversion quence. For our analysis, we will assume that the most significant bit (MSB) capacitor has a value of 20 pF. The capacitor nearest to the MSB capacitor will have half its value, or 10 pF and the least significant bit (LSB) capacitor will have one-quarter of the MSB capacitor value, or 5 pF.
A termination capacitor has the same value as the LS
B capacitor. The effect of this is that the sum of all the capacitors below the MSB capacitor becomes 20 pF, or the same value as the MSB capacitor.
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The positive analog input, VIN+, is sampled by the MSB capacitor through switch S2 and the capacitive conversion network, compod of three capacitors and two switches (S5 and S6). The negative analog input, VIN-, is sampled by two MSB-valued capacitors in ries through switch S1. The two analog inputs, positive and negative, permit this ADC converter to sample differential signals.
this means warThe reference voltage is applied to the REFIN input, internally buffered and distributed to all switches that are part of the conversion process. Switches S3 and S4 are connected to the buffered Vmid voltage. The value of Vmid is approximately 2.4 V with a 5-V supply; it will vary in direct proportion with the supply voltage. This buffer is important for proper charge distribution during the sampling period.
The comparator input signals are connected in parallel to switches S3 and S4. During conversion, the comparator output will be procesd by the control logic, which will properly t up switches S2,
S5 and S6. (Note that this type of architecture is for the ADS8361 and similar, bipolar input range parts. Other parts may have a similar structure, but are not identical.)
2. The Sampling Process in Detail
At the end of the conversion process, the ADS8361 automatically goes into the sampling process. The positions of switches S5 and S6 in the capacitive conversion network are unknown, as well as the position of switch S2. Switch S2 can be clod to either ground or the reference voltage. The status of the switches depends on the results of the previous conversion.
Fig. 2: Beginning of the Sampling Period
We know that switch S1 is connected to the reference voltage, VREF. The sampling process initiates closing switches S3 and S4. This short-circuits the comparator inputs and connects them to VMID. This initial pha of the sampling cycle is shown in Fig. 2.
britaBecau the positions of switches S5 and S6 are unknown, the equivalent capacitance of the network is also unknown. For proper sampling, however, the capacitive conversion network must have an equivalent capacitance that is equal to the MSB capacitor value. To obtain this capacitance, switches S5 and S6 in this step must connect the associated capacitors to the ground terminal. In this way, the positive input, as well as the negative input, of the comparator will be connected over the MSB capacitor equivalent value to ground. This configuration is shown in Fig. 3.
经典英文老歌Fig. 3: Retting the Value of the Capacitive Conversion Network
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Up to this point, all changes (such as charge distribution and switch positions) only affect the internal operation. The analog input signals were not affected by the changes. In the next step, input switches S1 and S2 clo, and the input signal is sampled on the input MSB capacitors. This period is the most critical period and to have accurate results from the conversion, the input buffer must be capable of charging the sampling MSB capacitors to the proper value. The sampling of the input signal is shown in Fig. 4.
Fig. 4: Sampling of the Input Signal大学英语六级听力
After charging the sampling capacitor with the input voltage, preparation for the conversion cycle starts with opening switches S3 and S4 when the charge on the sampling capacitors will be frozen. Disconnecting the MSB capacitors from the analog inputs VIN+ and VIN- indicates the end of the sampling period. The next step connects the MSB capacitors with switches S1 and S2 to the reference voltage, VREF. Fig. 5 shows the end of the sampling period and the start of the conversion cycle.
Fig. 5: Start of the Conversion Cycle.
This reprentative analysis is for a 3-bit ADC, or a capacitive conversion network that is compod of three capacitors and two switches. This capacitive conversion network can be replaced with the real one (for N-bits SAR ADC) shown in Fig. 6.
Fig. 6: Capacitive Conversion Network for N-Bits SAR ADC
The sampling (or MSB) capacitor connected to switch S0 has the standard value, C. The capacitive
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conversion network, as prented in Fig. 6, has an equivalent capacitive value equal to the value of the MSB capacitor. For the N-Bit SAR ADC, the capacitive conversion network will be compod of N+1 capacitors and N switches.
The first capacitor has a value that is one-half of the standard MSB capacitor value, or (0.5*C). The cond capacitor has a value that is one-fourth the value of C, the third one has a value that is one-eighth the value of C, and so on. The last two capacitors each have a value that is (1/2N) of the value of C. For a 12-bit SAR ADC, N is 12; for a 14-Bit SAR ADC, N is 14, and so on.
The resolution of the SAR ADC is equivalent to the number of switches and capacitors that are in the capacitive conversion network, and their respective values.
