SYNOPSYSVCS常⽤命令使⽤详解VCS对verilog模型进⾏仿真包括两个步骤：
1. 编译verilog⽂件成为⼀个可执⾏的⼆进制⽂件命令为：vcs source_files
2. 运⾏该可执⾏⽂件：./simv
类似于NC, 也有单命令⾏的⽅式：vcs source_files -R
-R 命令表⽰, 编译后⽴即执⾏。
vcs常⽤的命令选项如下：
-cm line|cond|fsm|tgl|obc|path 设定coverage的⽅式
+define+macro=value+ 预编译宏定义
-f filename RTL⽂件列表
+incdir+directory+ 添加include ⽂件夹
-I 进⼊交互界⾯
-
l logfile⽂件名
-P pli.tab 定义PLI的列表(Tab)⽂件
+v2k 使⽤推荐的标准
-y 定义verilog的库
-notice 显⽰详尽的诊断信息
-o 指定输出的可执⾏⽂件的名字，缺省是simv
+ nospecify 不对SPECIFY 模块进⾏时序检查和路径延时计算
+ notimingcheck 不进⾏时序检查；但是还是把path延时加⼊仿真中
Summary of vcs compile options:
-ASFLAGS "opts" pass 'opts' to the asmbler
-B generate long call instructions in native asmbly code (HP only)
-
CC "opts" pass 'opts' to C compiler
-CFLAGS "opts" pass 'opts' to C compiler
-LDFLAGS "opts" pass 'opts' to C compiler on load line only
-I enable interactive/postprocessing debugging capabilities
-ID get host identification information
-M enable incremental compilation (e manual)
-Mupdate enable incremental compilation and keep the Makefile up-to-date
-Marchive[=N] create intermediate libs to reduce link line length; N objs per lib
-P plitab compiles ur-defined pli definition table 'plitab'
-PP enable optimizer postprocessing capabilities for vcd+
-R after compilation, run simulation executable
-
RI after compilation, run simulation under xvcs (Implies -I)
-RIG run simulation under xvcs without compiling (executable has to exist)
-RPP run xvcs in postprocessing mode (requires file created by vcdpluson)
-V[t] verbo mode; with 't', include time information
-as foo u foo as the asmbler
-cc foo u foo as the C compiler
-cpp foo u foo as the C++ compiler
-e specify the name of your main() routine. (e manual ction 7-11 for more details).
-f file reads 'file' for other options
-gen_c generate C code (for HP and Sun, default is -gen_obj)
-gen_asm generate native asmbly code (HP and Sun only)
-
gen_obj generate native object code (HP and Sun only)
-ld foo u foo as the linker. (refer vcs manual for compatibility with -cpp option) -line enable single-stepping/breakpoints for source level debugging
-lmc-swift include lmc swift interface
-lmc-hm include lmc hardware modeler interface
-vera add VERA 4.5+ libraries
-vera_dbind add VERA 4.5+ libraries for dynamic binding
-location display full pathname to vcs installation for this platform.
-vhdlobj generate a vhdl obj for simulating in a vhdl design
-mixedhdl include MixedHDL-1.0 interface
-mhdl include MixedHDL-2.0 interface and library
-q quiet mode
-platform. display name of vcs installation subdirectory for this platform.
-syslib 'libs' specify system libraries (placed last on the link line) eg -lm
-o exec name the executable simulation model 'exec' (default is 'simv')
-u treat all non text string characters as upperca
-v file arch for unresolved module references in 'file'
-y libdir arch for unresolved module references in directory 'libdir'
+acc enable pli applications to u acc routines (e manual)
+ad include anlog simulation interface and library
+adfmi="files" ADFMI support for vcs-ace
+cliedit enable command line edit/recall (e doc/readline.ps)
+cli enable command line interactive debugging (e manual)
+cmod Enabling cmodule feature
+cmodext+cmodext Changing cmodule extension to cmodext
+cmodincdir+cmoddir Cmodule Include directory
+cmoddefine+macro define cmodule source 'macro' in the form. of XX=YY
+define+macro define hdl source 'macro' to have value "macro"
+plusarg_save hardwire the plusargs, which follow this flag, into simv
+plusarg_ignore turn off +plusarg_save
+prof tells vcs to profile the the design and generate vcs.prof file
+race tells vcs to generate a report of all race conditions and write this report in the race.out file
+rad+1 enable level 1 radiant optimizations (See Relea Notes)
+rad+2 enable level 2 radiant optimizations (See Relea Notes)
+libext+lext u extension 'lext' when arching library directorys
+librescan arch from beginning of library list for all undefined mods
+incdir+idir for `include files, arch directory 'idir'
+nospecify suppress path delays and timing checks
+notimingchecks suppress timing checks
+optconfigfile+foo u 'foo' as the optimization config file (See Relea Notes)
+vcsd enable the VCS Direct sim kernel interface
-cmhelp enable CoverMeter help
-cm enable VCS to first run cmSource to instrument the Verilog source files on the command line -cm_all enable VCS to link CoverMeter into the VCS executable in a way that enables all coverages
-cm_lineonly enable VCS to link CoverMeter into the VCS executable in a way that only enables line
coverage
[cpp]月份英文缩写
01. +v2k
02. Enables language features in the IEEE 1364-2001 standard.
[cpp]
01. success报告成功匹配
02. Enables reporting of successful matches, and success on
03. cover statements, in addition to failures. The default is to report
04. only failures.
05.
06.
07. filter过滤掉空成功。
08. Blocks reporting of trivial implication success. The happen
09. when an implication construct registers a success only becau
10. the precondition (antecedent) portion is fal (and so the
11. conquent portion is not checked). With this option, reporting
12. only shows success in which the whole expression matches.
13.
14.
15. -asrt filter+success经常两者结合起来⽤。注意⽤时在filter+success前加上-asrt
16.
17. maxsuccess=N
18. Limits the total number of reported success to N. You must
19. supply N, otherwi no limit is t. VCS continues to monitor
20. asrtions even after the limit is reached.
21.
22. -asrt maxsuccess=3
23.
24. -l filename logfile⽂件名
25. Specifies a file where VCS records compilation messages. If you
26. also enter the -R or -RI option, VCS records messages from both
sweep2wake
27. compilation and simulation in the same file.
28.
29.
30. -asrt enable_diag
31. Enables further control of results reporting with runtime options
32.
33. -sverilog
34. Enables the u of SystemVerilog code.
35.
36. -cm asrt
长颈鹿美语
37. Compiles for SystemVerilog asrtions coverage. -cm is not a
38. new compile-time option but the asrt argument is new. This
39. option and argument must also be entered at runtime.
40.
41.
42.
43. vcs *.v *.sva -sverilog \
44. +define+enable_blk_asrtions \
45. +define+tb_sva \
46. +define+slv_fc \
47. +define+slv_doc \
48. -PP -asrt enable_diag -cm asrt \
49. -l compile.log
50.
thelma and loui
51.
52. simv -l run.log -asrt filter+success -asrt maxsuccess=3
小学三年级英语下册53.
54. VCS对verilog模型进⾏仿真包括两个步骤:
55. 1. 编译verilog⽂件成为⼀个可执⾏的⼆进制⽂件命令为:
56. {1}gt; vcs source_files
57.
58. 2. 运⾏该可执⾏⽂件
59. {1}gt; ./simv
60.
61. 类似于NC, 也有单命令⾏的⽅式:
62. {1}gt; vcs source_files -R
63. -R 命令表⽰, 编译后⽴即执⾏.
64.
65.
66. -cm line|cond|fsm|tgl|obc|path 设定coverage的⽅式
67.
68.
69. A few more compile options are significant:
70. 1. if RVM class libs are ud in the OV code, this is required:
71. -ntb_opts rvm
72. 2. VMM class, vmm_ macros can be ud in SV; and rvm_ macros
73. in OV package are automatically translated to vmm_ equivalents if
74. this is also added
75. -ntb_opts interop -ntb_opts rvm
76.
77. -lca
78. 这是VCS的参数，表⽰使⽤VCS的“⽤户限制使⽤”的功能，即VCS提供的⼀些功能是他们还没有经过充分测试还没有发布的；如果你想使⽤这
怎么考人力资源证些功能就要加上 -lca参数。
79.
80. +incdir+directory
81. Specifies the directory or directories that VCS arches for include
82. files ud in the `include compiler directive. More than one
83. directory may be specified, parated by +.
84.
85. +plusarg_save
86. Some runtime options must be preceded by the +plusarg_save
87. option for VCS to compile them into the executable. You can
88. specify this option either on the vcs command line or in the file
89. specified with the -f or -F option.
90. You can also enter the following runtime options on the vcs command
91. line or in the file that you specify with the -f or -F compile-time option,
92. so that VCS compiles them into the simv executable, BUT you must
93. precede them with the +plusarg_save compile-time option:
94. +cfgfile +override_model_delays
95. +vcs+dumpoff +vcs+dumpon
96. +vcs+dumpvarsoff +vcs+grwavesoff
97. +vcs+ignorestop +vcs+learn+pli
98. +vcs+mipd+noalias +vcs+nostdout
99. +vcs+stop +vera_load
100. +vera_mload +vpdbufsize
101. +vpddrivers +vpdfile
102. +vpdfilesize +vpdnocompress
郑东河103. +vpdnostrengths +vpdports
104. +vpdupdate
105.
106. -ntb_opts dtm
107. You enable testbench constructs outside programs with the
108. -ntb_opts dtm compile-time option and keyword argument.
109. The testbench constructs that you can enter outside programs with 110. this option are as follows:class associative arrays dynamic arrays 111. SystemVerilog named events
⼯作状态: 建⽴仿真环境
VCS是Synopsys公司的仿真⼯具.
VCS对verilog模型进⾏仿真包括两个步骤:
1. 编译verilog⽂件成为⼀个可执⾏的⼆进制⽂件命令为: $> vcs source_files
2. 运⾏该可执⾏⽂件
$> ./simv
类似于NC, 也有单命令⾏的⽅式:
$> vcs source_files -R
-R 命令表⽰, 编译后⽴即执⾏.
下⾯讲述常⽤的命令选项:2013年英语四级
-cm line|cond|fsm|tgl|obc|path 设定coverage的⽅式
+define+macro=value+ 预编译宏定义
-f filename RTL⽂件列表
+incdir+directory+ 添加include ⽂件夹
-I 进⼊交互界⾯
-l logfile⽂件名
-P pli.tab 定义PLI的列表(Tab)⽂件
食品安全专业+v2k 使⽤推荐的标准
-y 定义verilog的库
take one-notice 显⽰详尽的诊断信息
-o 指定输出的可执⾏⽂件的名字，缺省是sim.v
