Product Brief
August 2000
ATM UTOPIA Slave Core V2.0
Features
s UTOPIA Level 1/Level 2 with parity generation/ checking. In Level 2, all multi-PHY modes are sup-ported:
— 1 RxClav/1 TxClav
— Direct status
— Multiplexed status polling
s8-/16-bit bus width
s Programmable cell length
s25/33/50 MHz operation
s Meets all UTOPIA tup and clock-to-output speci-fications
s FIFO control/monitoring with the following options:— Internal 128 × 9/64 × 17 ORCA® FIFOs (scal-able)
s Flexible control inputs with options for the follow-ing:
— Internal/external hardwiring
within and without— Access via a parallel or rial microprocessor interface
s Supports the ORCA Series 2 and Series 3 families of FPGAs
Standards Compliance
s A TM forum UTOPIA Level 1 version 2.1
s A TM forum UTOPIA Level 2 version 1.0 Benefits
s Faster development for improved time-to-market with ATM functions
s Lower development cost through design reu s VHDL* source code for easy design integration
s ORCA-specific optimization, tailor-made for high performance
s Ample design flexibility using built-in interface and function options
s Verified functionality and standards compliance
0390(F) Figure 1. ATM UTOPIA Slave Core Application Description
The ATM UTOPIA Slave Core from Modelware†implements, in modular VHDL, the ATM forum's UTOPIA Level 1 and Level 2 specifications.
The core interfaces to the application (e.g., ATM physical or adaptation layer) via a generic FIFO-like access interface and to the ATM layer via a UTOPIA Level 1 or Level 2 interface (Figure 1). The core us internal FIFOs for cell buffering and timing transfer between the application and the ATM layer.
The core (using 18-bit internal FIFOs) operates at 50 MHz in an OR2T15A-6 or an OR3T55-7 ORCA FPGA.
*VHDL is a registered trademark of Gateway Design Automation Corporation.
†Modelware is a registered trademark of Modelware, Inc.
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ATM UTOPIA Slave Core V2.0
Lucent T echnologies Inc. rerves the right to make changes to the product(s) or information contained herein without notice. N o liability is assumed as a result of their u or application. No rights under any patent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent T echnologies Inc.
Copyright © 2000 Lucent T echnologies Inc.All Rights Rerved
初三英语上册August 2000PB00-087NCIP
For additional information, contact your Microelectronics Group Account Manager or the following:
法语出国考试INTERNET:
/micro , or for FPGA information, /orca E-MAIL:
docmaster@ N. AMERICA:Microelectronics Group, Lucent T echnologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18109-32861-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA P ACIFIC:Microelectronics Group, Lucent T echnologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256Tel. (65) 778 8833, FAX (65) 777 7495CHINA:Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Univer Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652JAP AN:Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700EUROPE:Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
T echnical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid)
Product Brief August 2000
Design Package
The A TM UTOPIA slave core package contains:
s VHDL source code s VHDL testbench
s
Scripts and data files for simulation (behavioral and gate-level), synthesis, and FPGA layout
s
ahmadDetailed documentation:
— Reference guide: features, architecture, inter-faces, and operation
— Ur's guide: simulation, synthesis, and FPGA layout procedures
Required Tools
s MTI V-system for simulation
s Exemplar LeonardoSpectrum * for synthesis
s
Lucent T echnologies ORCA Foundry for FPGA layout
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*Exemplar and LeonardoSpectrum are trademarks of Exemplar Logic, Inc.
attendAdditional Resources
s
ORCA ATM Physical Layer CSC Application Note (AP97-050FPGA available from Lucent Technolo-gies)
s
ORCA OR2CxxA and OR2TxxA Series Field Pro-grammable Gate Arrays Data Sheet (DS98-022), January 1998
s ORCA OR3CxxA and OR3TxxA Series Field Pro-grammable Gate Arrays Data Sheet (DS98-163-1), August 1998
s
Asynchronous Transfer Mode: ATM Architecture and Implementation , Martin et al., Prentice Hall 1996
Ordering Information
Modelware, Inc.T el: (732)936-1808Fax: (732)936-1838
E-mail: Internet:
