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Features
•
100MHz (200 MIPs) Zarlink voice processor with Butterfly hardware accelerator and breakpoint/interrupt controller
•On-board Data (26 Kbytes), Instruction (24 Kbytes RAM and Boot (3 Kbytes) ROM •Dual ∆Σ ADCs with input buffer gain lection programmable to either 8 or 16kHz sampling •Dual ∆Σ DACs with output sampling of 8, 16, 44.1 and 48kHz and internal output driver
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•2048 tap Filter co-processor shared across up to 16 parate functions in 128 tap increments •
Dual function Inter-IC Sound (I 2S) or Secondary TDM port
•
Primary PCM port supports TDM (ST BUS, GCI or McBSP framing) or SSI modes at bit rates of 128, 256, 512, 1024, 2048, 4096, 8192 or 16384 Kb/c •Separate slave (microcontroller) and master (Flash) SPI ports, maximum clock rate = 25MHz •Watchdog and 2 auxiliary timers
•11 General Purpo Input/Output (GPIO) pins •General purpo UART port
impacted•Bootloadable for future Zarlink software upgrades •External oscillator or crystal/ceramic resonator • 1.2V Core; 3.3V IO with 5V-tolerant inputs •
IEEE-1149.1 compatible JTAG port
June 2006
Ordering Information
ZL38004QCG1
100 Pin LQFP Trays, Bake & Drypack
*Pb Free Matte Tin -40°C to +85°C
ZL38004
Dedicated Voice Processor with Dual Channel Codec
Data Sheet
Figure 1 - Functional Block Diagram
Data RAM
DSP Boot ROM
Instruction RAM 27K Bytes
24K Bytes 3K Bytes Interrupt Controller ButterFly Hardware Accelerator
DAC
Buffer
ADC Driver CODEC[0]IRQ[15:0]
IRQ
DAC
Buffer
ADC Driver
CODEC[1]
IRQ PCM P0
I 2S
Filter
Co-processor
Watchdog Master SPI Slave SPI UART GPIO
AUX Timer1AUX Timer2
IRQ IRQ
APLL MCLK
OSC
JTAG
IRQ
APLL
Timing Generator
100 MHz MCLK
CODEC[1:0]IRQ
IRQ不知道的英文
IRQ
IRQ
IRQ
IRQ
two months
IRQ
IRQ
Device Clocks
Chain
OSCi OSCo
PCM_CLKi日语真题
PCM_LBCi
5/
5/
4/
2/11/
5/
5/
Core
PCM P1
PCM P0Clock
Applications
fortune500•Hands-free car kits
•Full duplex speaker-phone for digital telephone
•Echo cancellation for video conferences
•Intercom Systems
•Security Systems
1.0 Functional Description
The ZL38004 is a hardware platform designed to support advanced acoustic echo canceller (with noi reduction) firmware applications available from Zarlink Semiconductor. The applications are resident in external memory and are down-loaded by the ZL38004 resident boot code during initialization.mentholatum
The firmware products and manuals available at the relea of this data sheet are: ZLS38500: Acou
stic Echo Canceller with Noi Reduction for Hands-Free Car Kits; ZLS38501 Speakerphone. If the applications do not meet your requirements, plea contract your local Zarlink Sales Office for the latest firmware releas.
The ZL38004 Advanced Acoustic Echo Canceller with Noi Reduction platform integrates Zarlink’s Voice Processor (ZVP) DSP Core with a number of internal peripherals. The peripherals include the following:
•Two independent ∆Σ CODECs
•Two PCM ports - ST BUS, GCI, McBSP or SSI operation
•An I2S interface port
• A 2048 tap Filter Co-processor
•Two Auxiliary Timers and a Watchdog Timer
•11 GPIO pins
• A UART interface
• A Slave SPI port and a Master SPI port
• A timing block that supports master and slave operation
•An IEEE - 1149.1 compatible JTAG port
The DSP Core can process up to four 8-bit audio channels, two 16-bit audio channels or two 8-bit and one 16-bit audio channel. The audio channels may originate and terminate with the Σ∆ CODECs, or be communicated to and from the DSP Core through the PCM ports or the I2S port.
2.0 Core DSP Functional Block
The ZL38004 DSP Core functional block, illustrated in Figure 1, is made up of a DSP Core, Interrupt Controller, Data RAM, Instruction RAM, BOOT ROM and a ButterFly Hardware Accelerator. This block controls the timing (APLL and Timing Generator), peripheral interfaces and Filter Co-processor through a peripheral address/data/control bus and 16 prioritized interrupts.
The ZL38004 implementation of DSP core and Filter Co-processor have been optimized to efficiently support voice processing applications. The applications are described in detail in the firmware manuals associated with this hardware platform.
When an interrupt occurs the DSP core saves its current status and jumps to the address of the associated interrupt rvice routine.
3.0 Codec[1:0]
The ZL38004 has two 16-bit fully differential ∆Σ CODECs (CODEC 0/1) that can be programmed for 48kHz or 44.1kHz sampling, or to meet G.712 requirements at 8kHz sampling or G.722 at 16kHz sampling, e Figure 2. The ADC path consists of input signal pins C0/1_ADCi+ and C0/1_ADCi- (buffer output pins C0/1_BF0+ and C0/1_BFo-), which feed lectable Microphone Amplifier or Line Amplifier options. Once past the buffer the analog signal goes through a low pass antialiasing filter and to a 4th order feed-forward ∆Σ Modulator that produces a Pul Density Modulated (PDM) signal. Next the PDM signal goes through a Low Pass Decimation Filter and then is converted into a 16-bit parallel word that can be read by the ZL38004 DSP (ADCout[15:0], Figures 2).
The ZL38004 DSP will nd 16-bit parallel word samples (DACin[15:0], Figure 2) to the DAC where they are converted to rial data and pasd through an interpolation filter followed by a digital ∆Σ Modulator. The ∆ΣModulator generates PDM data, which then pass through a 32-tap FIR reconstruction filter. The reconstructed analog signal is then pasd to a unity voltage gain differential output driver and to pins C0/1_DACo+ and C0/1_DACo-.
The CODEC bias voltages are generated by an internal bandgap circuit (BIAS_VCM, BIAS_RF+ and BIAS_RF-).
Each ZL38004 CODEC has two loopbacks. When activated, the input analog signal on pins C0/1_ADC+/- is looped around to C0/1_DAC+/-. Pul Density Modulated (PDM) rial data from the ADC Analog ∆Σ Modulator output is looped around to the input of the DAC Reconstruction Filter. At the same time 16-bit parallel data is looped around from DACin[15:0] to ADCout[15:0]. PDM rial data from the DAC Digital ∆Σ Modulator is looped around to the input of the ADC Digital Low Pass Decimation Filter.
When the Parallel Loopback is activated the input analog signal on pins C0/1_ADC+/- is looped around to the C0/1_DAC+/- output. 16-bit parallel data from the ADC Digital Low Pass Decimation Filter is looped around to the DAC Digital Low Pass Interpolation Filter. This data may be read by the DSP, but parallel data written to the DAC by the DSP will be lost.
CODEC0 and CODCE1 of the ZL38004 may be powered down if they are not required. See firmware manual.
Figure 2 - CODEC Block Diagram
4.0 PCM / I 2S Ports
The PCM ports 0 and 1 support data communication between an external peripheral device and the ZL38004 DSP Core using parate input (P0/1PCMi) and output (P0/1PCMo) rial streams with TDM (i.e., ST-BUS, GCI or McBSP) or SSI interface timing in both master or slave timing modes. Both PCM Ports 0 and 1 support the same functionality and modes of operation.
PCM Port 1 pin functions are shared with the I 2S Port pin functions. The I 2S (Inter-IC Sound) port and PCM Port One share the same physical pins of the ZL38004. Selection of either I 2S port operation or PCM Port One operation is done through the Port One PCM/I 2S Select Register. See firmware manual.
The I 2S port can be ud to connect external Analog-to-Digital Converters or CODECs to the internal DSP . This port can operate in master mode, where the ZL38004 is the source of the port clocks, or slave mode, where the bit and sampling clocks (I 2S_SCK and I 2S_ LRCK) are inputs to the ZL38004. In I 2S port master mode the clock signal at output pin I 2S_LRCK is the sampling frequency (f S ), the clock signal at output I 2S_SCK is 32 x f S , and the clock signal at output I 2S_MCLK is 256 x f S . In I 2S port slave mode the relationship between the clock signal at input pin
I 2S_LRCK and the clock signal at input I 2S_SCK must be 32 x f S . In slave mode the 256 x f S relationship between f S and the I 2S_MCLK is not mandatory, and the I 2S_MCLK output pin will be in a high impedance state.Access to the control and status registers associated with the ports is through the Slave SPI port or UART.
Buffer
Analog ∆ΣModulator
Digital LP Decimation Filter
Digital LP Interpolation
Filter
Antialiasing
Filter
Bias Generation
16unusual
1616
Reconstruction Filter & Driver
Digital ∆ΣModulator 3.0720 MHz 2.8224 MHz
Analog Clock
Analog Clock
CODEC Loopback
CODEC Loopback
Parallel BIAS_VCM BIAS_RF+BIAS_RF-C0/1_BFo+C0/1_BFo-C0/1_ADCi+C0/1_ADCi-C0/1_DACo+C0/1_DACo-
DACin
[15:0]
ADCout [15:0]
Analog Clock Select
ZL38004
PDM CODEC Loopback
PDM
5.0 Host Microprocessor and Peripheral Interfaces
The ZL38004 provides 1 master SPI port (with 2 chip lects), 1 slave SPI ports and an UART. The master SPI port’s primary function is to access and external FLASH memory to download firmware to the ZL38004.
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The control/status registers and memory of the ZL38004 can be accesd (R/W) by an external host through the Slave SPI and the UART ports. Register/Memory read and write access are carried out through a ries of port read and write access as follows:
5.1 Master SPI (FLASH Port)
The Master SPI port is ud by the ZL38004 to access one or two peripheral devices (chip lect signals SPIM_CS[1:0]). It supports both SPI and MICROWIRE modes of operation and can write up to 40 bits or read up to 32 bits in a single access. The Chip Select output signals may be programmed for a single access or burst access. All communication is MSB first and all pins of the master SPI port are outputs controlled by the ZL38004, except SPIM_MISO.
5.2 Slave SPI (Host Port)
The slave SPI port may be ud by an external host microprocessor to access (Read/Write) the ZL38004 internal control/status registers and memory. Access is initiated when the external host makes signal SPIS_CS low and is ended when this signal goes high. The host will then apply a clock (maximum 25 MHz) to signal SPIS_CLK to clock data out of SPIS_MISO and in on SPIS_MOSI.最喜欢的英文
5.3 UART
The UART (Universal Asynchronous Receiver Transmitter) port may be ud by an external host microprocessor to access (Read/Write) the ZL38004 internal control/status registers and memory. The ZL38004 DSP will t up the initial parameters of this port (i.e., master/slave, baud rate, stop bits, ) during the Boot process. After the device has been booted the port options can b
e changed as per the firmware manual.
The UART port will support 8-bit data only with any combination of 1 start bit, 0 or 1 parity bit(s) and 1, 1.5 or 2 stop bit(s).
The ZL38004 has 11 GPIO (General Purpo Input/Output) pins that can be individually configured as either input or output. The pins are intended for low frequency signalling.
When a GPIO pin is defined as an input the state of that input pin is sampled with the internal master clock (Mclk = 100 MHz) and latched into the GPIO Read Register. This sampling can be stopped (Freeze) on an individual GPIO pin. Individual pins of GPIO[4:0] may have an internal pull-down resistor activated/deactivated and individual pins of GPIO[10:5] may have an internal pull-up activated/deactivated.
Immediately after a power-on ret (RST pin) the GPIO pins are defined as inputs and their state is captured in the GPIO Start-Up Status Register. The state of this register is ud by the Boot program to determine the ba functionality and programming options of the device.
Individual GPIO pins may also be defined as outputs with associated enable/disable (active/high impedance) control.
