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Frequently Asked Questions:
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MIPI Alliance Standard for D-PHY v0.65
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Version 0.65 – 26 July 2006
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Copyright © 2006 MIPI Alliance, Inc. All rights rerved.
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The material contained herein is not a licen, either expressly or impliedly, to any IPR owned or controlled 8
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by any of the authors or developers of this material or MIPI. The material contained herein is provided on 10新片速递
an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS 11
AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all 12
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negligence.
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ALSO, THERE IS NO WARRANTY OR CONDITION OF TITLE, QUIET ENJOYMENT, QUIET
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POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD 19
TO THIS MATERIAL. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE
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Questions pertaining to this document, or the terms or conditions of its provision, should be addresd to: 28
MIPI Alliance, Inc.
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c/o IEEE-ISTO
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Attn: Board Secretary
Frequently Asked Questions:
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MIPI Alliance Standard for D-PHY v0.65
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List of FAQ items
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1.D-PHY Specification version 0.65 versus 1.0
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a.Why is the first relea of D-PHY called “v0.65” rather than “v1.0”?
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b.Is the number 0.65 significant?
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c.What changes are expected after v0.65?
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2.Bit Error Rate (BER)
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a.Why is there no specification of BER in the D-PHY specification
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document?
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b.Many other PHY specifications include BER values, so why doesn’t D-
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PHY?
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c.How is a BER “target” different from a specified value?
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d.Does the BER target apply to the CLOCK lane as well as the DATA lane?
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e.Will a single D-PHY lane have only single bit errors or will multi-bit
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bursts occur?
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f.How is the target BER of 10e-12 calculated?
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g.Is a burst of external interfering noi that caus a single bit error on one
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data lane likely to affect other data lanes of a multi-lane D-PHY
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(automatically causing a multibit error in a transmission)?
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h.Would the CLOCK lane also have a BER of 10e-12?
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i.Could an error on the CLOCK lane corrupt more than one bit in the
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reception of the associated data packet?
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3.Why are there two low power modes (LP and ULP)?
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4.Why does D-PHY not specify any clock system?
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5.High Speed sync quence
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a.How robust is the high speed SoT synchronization quence?
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b.How many bits should the receiver u to detent sync?
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c.Can I build a receiver that is tolerant of two or more bit errors in the sync
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quence?
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6.Will DZolp(01,10) be removed from the D-Phy specification after v0.65?
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7.Normative requirements in D-PHY for End of Transmission [EOT] processing
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a.EOT processing is normative in the D-PHY specification (ction 5.4.3)
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when this operation can be done outside the D-PHY for some protocols?
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EOT processing in the D-PHY requires a data buffer, which is not ideal for 70
an I/O function.
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8.Interoperability
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a.How can I calculate the maximum operating data rate for a pair of
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components from their documented values of Maximum Data Rate and 74
UIinst(min)?
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Q. Why is the first relea of D-PHY called “v0.65” rather than “v1.0”?
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A. D-PHY v0.65 reprents a specification effort that is nearly complete, but not yet
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tested in silicon and therefore “subject to change.” The MIPI Phy Working Group 80
intends the first “one point zero” relea of the D-PHY Specification to offer all MIPI 81
members the confidence of an interoperable design proven in silicon by veral 82
miconductor companies. Therefore, the WG prefers not to u the major milestone of 83
version 1.0 if a member company has not yet put that Spec relea through fabrication.
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The MIPI Board supports this approach.
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Even so, the relea of D-PHY v0.65 is a major milestone that offers the industry a lot of 87
value. There is significant material in the Spec that allows a MIPI member company to 88
begin work on a physical layer. It derves to be relead in a licensable form to allow
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companies to begin if they desire.北京雅思家教
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Neither the Board nor the Phy WG wants to limit exposure of the D-PHY Specification 92
while work is ongoing toward a 1.0, which is expected during 2007. MIPI expects that
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some Board, Contributor, and Adopter companies will all begin work on D-PHY
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implementations now, and it is hoped that the experiences can be ud to finalize a 1.0.
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Q. Is the version number 0.65 significant? Is the Spec “65% done?”
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A. The number has no relation to the state of completeness. The MIPI board considers
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the completeness of D-PHY v0.65 well above 65%, ready enough for member companies 100
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to begin preliminary implementations.
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We are all familiar with other standards organizations that u specific version numbers 103
to indicate specific milestones, but in general Phy WG has chon not to proceed with 104
this approach. The WG simply incremented the version number by 0.01 with each new 105
draft of the spec, whether the changes were significant or minor.
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Q. What changes are expected after v0.65?
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A. The Phy Working Group does not expect to change any basic concepts or the
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functions performed by the PHY as it works toward v1.0. Nonetheless, discussion and 111
work continues, and the WG has identified some expected changes to some details in the 112
Spec.
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Where practical, the WG has documented expected areas of change in a “D-PHY v0.65 115
Relea Notes” companion document available to all MIPI members in the same Web 116
directory as the D-PHY Specification. The first relea of this document occurred on 1 117
December 2005, and the document will be updated as necessary, though infrequently, 118新标准小学英语
on the path to v1.0. In some cas, the document suggests the direction of a change to D-119
PHY v0.65 that is expected for v1.0.
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Plea keep in mind that until a new Specification is officially approved, the Relea
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Notes should be considered as informative, not an authoritative list of “approved” Spec 123
changes. The topics in the Relea Notes are actively being discusd, and any suggested 124
modifications in the Relea Notes are subject to change.
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Q. Why is there no specification of Bit Error Rate (BER) in the D-PHY
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specification document?
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A. The measurable BER of a D-PHY depends on the complete implementation. Since the 130
Specification cannot control all implementation details without placing unusual burdens 131
and cost on all implementers, D-PHY makes it possible for implementers to achieve a 132
high level of robustness on the link if care is taken in all areas of the implementation. 133
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The required level of robustness was t by cooperative discussion between MIPI PHY 135
and protocol working groups (such as Camera and Display WG’s) who discusd basic 136
requirements for a physical layer. The PHY WG was given the target of specifying a link 137
capable of a BER equal to or better than 10e-12.
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Phy WG achieved this requirement by tting specifications on signal levels (especially 140
the signal level difference between a logical “0” and “1”) and timing margins as en at 141
the receiving end of an interconnect network. The specified values allow the design of 142
a robust implementation across variations in miconductor process, temperature and 143
supply voltage that can easily exceed this BER target in the abnce of externally coupled 144
noi.
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External noi may be coupled into the link via the power, ground or signal
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interconnects. Its net effect is to degrade the signal and timing margins, creating a
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higher probability of the receiver mis-sampling the transmitted data. D-PHY v0.65
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specifies a t of interconnect values sufficient to insure transmission of signaling
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frequency components and attenuation of non-signaling, i.e. interfering components. 151
However, external noi sources occur in the signaling frequency bands [depending on 152
data rate] and will therefore introduce signal degradation and potentially errors. It is the 153
system integrator, i.e. application designer, who must balance the cost of the
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interconnect, power supply integrity, ground connections, and signal shielding while 155
considering the data-sheet noi rejection specifications of the transmitter and receiver 156
ICs. It is not within the scope of a PHY specification to make this tradeoff. It is the
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connsus of the PHY WG that robust implementations of D-PHY can be designed at 158
reasonable cost with error rates exceeding the target.
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Q. Many other PHY specifications include BER values, why not D-PHY?
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A. Tho specifications address topics that are out of scope either for MIPI 162
specifications, or for D-PHY in particular. For example, the MIPI Alliance does not 163
engage in compliance testing. Some of tho other PHY Specs include descriptions of 164
necessary compliance tests with BER limits such as “when transmitting PRBS 2e31 165
pattern over 40cm of 50 Ohm FR4 stripline, a BER of less than X must be achieved.” 166
Compliance specifications of this form are not part of the D-PHY Specification as 167
currently drafted, as per MIPI Board instruction.
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Q. Does the BER target apply to the CLOCK lane as well as the DATA lane? 170
A. The short answer is that BER is not a valid concept for the CLOCK lane. Clock lane 171
errors manifest themlves in a different form: they are a loss of coherence with the data 172
lane. A correct implementation of a source synchronous link maintains coherence 173
between the CLOCK and DATA lanes by launching the data with same clock edge put on 174
the CLOCK lane so that any instantaneous jitter in the clock is transferred to the data. 175
In this way, when the data and clock arrive at the receiver, the jitter deviation in the 176
CLOCK is coherent with the jitter deviation of the DATA and no timing margin is lost. 177
This requires very low skew between the clock and data lanes due to interconnect and 178
silicon delays. [Note that even source synchronous systems with DLL skew will adjust 179
the jitter transmitted through the DLL due to the high jitter transfer characteristics of 180
DLLs].
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The external noi coupling mechanisms for the CLOCK lane are the same as for the 182
DATA lane. The effect of the coupled noi as en at the receiver is to move the edges of 183
the clock relative to the data. A missing clock pul is conceptually an edge that has been 184
moved by more than one UI. A clock error occurs when a clock edge moves such that it 185
falls outside of the allowed fractional UI period jitter specification. Many factors will 186
determine if this will cau a data error. There is therefore a non-zero probability that a 187
clock error will not be obrvable to the ur.
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The total error rate of the PHY is therefore:
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P(data lane missampling data) = P(error due to data lane noi coupling) + P(clock edge moved out of spec) * P(moved clock edge caus sampling error in data lane).
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Q. Will a single D-PHY lane have only single bit errors or will multi-bit 191
bursts occur?
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coupA. Real world noi sources produce interfering signals over finite time intervals. If this 193
time interval is short relative to a bit time on the link, then it is likely to cau only a 194
single bit error per lane. If it is long relative to a bit time, then multibit error bursts are 195
likely to occur.
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Therefore the error characteristic of a lane operating under identical noi conditions is 197
dependent on the data rate. The higher the data rate, the more likely errors will have a 198
burst characteristic. It is for this reason that high speed links u CRC type error 199
correction consisting of polynomial, Reed-Solomon or LPC codes rather than simple 200
linear codes like Hamming codes.
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Q. How is the target BER of 10e-12 calculated?
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A. Just as the acronym indicates, this is a BIT error rate. The total number of bits 204
received in error is divided by the total number of bits transmitted. For this number to 205
be uful, an implicit Gaussian error distribution is required. As discusd above, given 206
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