一、TMAX的使用crayon怎么读
1. 工具接口
bothofthemBasic input of TetraMAX to perform ATPG are the vendor gate-level simulation libraries, design netlist, command script and test procedure file. Main output data are the test patterns and reports on results. In order to read in netlist and library files, u the “read netlist” c ommand or the Netlist button of the GUI. The netlist format (Verilog, EDIF, VHDL) is automatically detected. It is recommended you u Verilog as the netlist input format. TetraMAX also automatically detects netlist compression (none, GZIP, proprietary binary). A single file may contain one or more modules. By using multiple files, mixed language netlists are supported. A single read command may u wildcards to match multiple files using the …?‟ and …*‟ characters. Example:
read netlist /proj/mars/lander/shared/*/??DFF*.v
日语在线翻译中文
There is no restriction whether to u flat or hierarchical netlists.
Standards for pattern input: VCD-E, WGL, STIL.
Standards for pattern output: Verilog, WGL, STIL, VHDL.
Multiple pattern compression techniques (static & dynamic).
Built-in GZIP compression support for file inputs and outputs (designs, libraries, protocols, patterns, f
ault lists).
2. 使用流程
The diagram illustrates the basic test pattern generation flow. The three operation modes of TetraMAX are shown by different colors. During build mode the design and libraries are read in, and the ATPG model of the design is built. If the build step was successful, you automatically get into DRC (design rules checking) mode. Here you specify all information needed by the tool to configure the design for test. The test procedure file (STIL = Standard Test Interface Language) is read in. If DRC was successful, you get into Test mode. You finally adjust ttings for ATPG, start pattern generation, perform pattern compression and save the patterns to disk.
STEP:
(1) Reading the Library Files
U NETLIST button or read netlist command: BUILD> read netlist mylibrary.v Read netlists in hierarchy order, from library leaf cells (first) to top level module (last). Example:BUILD> read netlist /libs/0.18u/*/??DFF*.v
In ca of duplication when reading in netlists, the default behavior is to keep the last module definition encountered. Netlist type (Verilog, EDIF, VHDL) is automatically detected. Netlist compression (none, GZIP, proprietary binary) is automatically detected. A single file may have one or
more modules. A single read command may u wildcards to match multiple files us ing the …?‟ and …*‟ charac ters.
(2) Read Design Netlist
U NETLIST button or read netlist command:BUILD> read netlist my_asic.v Designs may be described using forms of:
Verilog structural netlists;
EDIF structural netlists;
VHDL structural netlists;
Mixtures of the above -- note: beware of naming convention restrictions of each language;
Netlists may be either flat or hierarchical;
Netlists may exist as a single file or multiple files.
(3) Build the ATPG Design Model
U NETLIST button or build model command: BUILD> run build_model my_asic The build process is ud to choo the top-level module and to build the in-memory design image necessary for the ATPG algorithm.
You may also build at any intermediate level. Synopsys recommends that you read in the library first, then the DUT netlist, otherwi, specify top-level in build command.
(4) Perform Design Rule Checks
U DRC button or run drc command: DRC> run drc DUT.spf
Scan Testing Rules Checked During DRC:
(S rules) The scan chains are checked for working order during shift mode and that the scan input to output path is logically connected.
(C rules) Clocks and asynchronous t/ret ports connected to scan flops are checked to e that they are controlled only by primary inputs.
(C rules) Clocks/ts/rets are checked for off state when switching from normal mode to scan shift mode and back again.
(Z rules) Multi-driver nets are checked for contention.
run drc in TetraMAX is nearly identical to dft_drc in DFT Compiler:
PI = Primary Input;
PO = Primary Output;
Constraint = a restriction to be honored when generating ATPG patterns;
Gate ID = unique integer assigned to each distinct ATPG primitive in the flattened design;
CLOCK = any signal that affects the stored state of a quential device including asynchronous ts and rets as well as RAM write controls.
(5) Prepare for ATPG
Running ATPG with ATPG button or run atpg command: TEST> run atpg -auto Always start with –auto. It provides the best starting point and tradeoff between coverage and pattern count in the current and future releas. Most (though not all) of the ATPG options are specified by the t atp
g command. The Run ATPG dialog box shown can invoke t atpg, run atpg, and other commands. A key choice on the dialog is fault model: click the radio button for one of three models, or run command: TEST>t faults –model stuck. Given the fault model, you can then inject all possible SAFs by clicking Add all faults, or run command:TEST>add faults -all. (6) Review Summary Report
U SUMMARY button or run summary command:
brimnegotiateSUMMARY> report summaries faults patterns > /* save_path/file_name.rpt Options to Report Summaries.
学会享受生活Primitives: Reports the ATPG primitive summary.
Faults: Reports the fault summary. The display of collapd versus uncollapd fault categories or normal versus verbo fault class detail is controlled by u of the t faults command.
Patterns: Reports the pattern count.
Library_cells: Reports the library cells. A report includes the name of the library cell and the number which have been instantiated in the flattened design. NOTE: This count may differ slightly from an ASIC vendor' s report of the same data due to circuit optimization done for ATPG purpos which ma
y result in the elimination of certain internal gates.
man in black
Memory_usage: Reports total RAM usage by the process and well as the RAM ud by the data space patterns + design of the process. NOTE: This report is available only on UNIX platforms.
Optimizations: Reports the gate optimization and removal performed during the run build process.
Sequential_depths: Reports the maximum Fast-Sequential depth for controlling, obrving, and detection, and a reprentative gate ID for each.
Cpu_usage: Reports the cumulative CPU usage since starting the tool for lected operations such as reading netlists, performing model builds, generating ATPG patterns, compressing patterns, etc.
(7) Saving ATPG Patterns
U WRITE PATTERNS button or run write patterns command:
WRITE PATTERNS >
write patterns /*save_path/ file_name.stil -replace -internal -format stil –rial There are many option
s for pattern output configuration. File Format specifies the format the patterns should be written with. Note that there are some more variations of Verilog, e. g. rial or parallel scan load, and VHDL or VHDL93. You can specify which pattern type to exclude from the pattern output. All types are written by default. By specifying a pattern range you can lect which patterns should be written to the file. This is uful for simulation and debugging purpos. If you need to generate multiple smaller pattern files instead of a single one containing all patterns, u the split option. You can further specify the type of data compression to be ud: none, GZIP, or Binary. Binary is a proprietary compression format.
(8) Verifying ATPG Patterns
Ensure Static Timing Analysis was correctly performed before simulating any ATPG patterns. Perform gate-level simulation in your sign-off environment.
二、高级命令解释
1. collapd
t faults -report collapd
The target coverage is affected by your u of the t fault -reportcommand. If fault reporting is t to collapd, the target percentage is in collapd fault numbers. If fault reporting is t to uncollapd, the target percentage is in uncollapd numbers. The test coverage obtained through the uncollapd fault list is usually higher and within a few percentage points of the test coverage obtained through the collapd fault list (note, however, test coverage can slightly more with the fault report t to collapd compared to the test coverge with fault coverage t touncollapd). To be conrvative, t fault reporting to collapd before you generate patterns for a specific target coverage. When you have finished, display the test coverage using the uncollapd fault list numbers. Often, the actual test coverage achieved will be higher than your target.英语四级准考证号忘记
2. ndetects
run atpg -ndetects 1
N-detection attempts to detect faults ntimes in ATPG. The default is one fault detection. During fault simulation, the fault is kept in the active list until it is detected ntimes. Studies have shown that detecting faults with multiple patterns helps catch defects that cannot be modeled with standard fault models. Examples include transistor stuck-open or cell-level faults.Pattern size, memory consumptio
n, and runtime will be larger than with the default one fault detection.With the exception of the IDDQ and path delay fault models, all other fault models are supported. Distributed processing, Full-Sequential ATPG, and fault simulation are not supported.
3. nsitive
t patterns external /*path/file_name.v –nsitive
TetraMAX automatically determines what type of netlist is referenced and reads the file to collect design and module descriptions. By default, Verilog netlists are treated as ca-nsitive; EDIF and VHDL netlists are treated as ca-innsitive. If you want to override the default, add-nsitive or-innsitive at the end of the command.
t patterns external /*path/file_name.v –nsitive
If you have some vectors in the external buffer before starting distributed ATPG, they
sniffy>剑桥商务英语初级
