交通灯Verilog设计

更新时间:2023-06-19 00:57:33 阅读: 评论:0

module traf_lamp(clk,en,lampa,lampb,acount,bcount);
input clk;
input en;//使能端高电平有效
output reg[3:0] lampa,lampb;//4位分别用于a灯的颜色选择output [7:0] acount,bcount;//分别用于驱动数码管显示
reg tempa,tempb;//用于控制路口红绿灯等的变换,低电平有效reg [7:0] numa,numb;//用于显示的数据值
reg [2:0] counta,countb;//表示灯的状态
reg [7:0] ared,agreen,ayellow,aleft,bred,bgreen,byellow,bleft;
引言是什么意思//各种灯计数器的预置数
always@(en)
if(!en) begin
ared <=8'd55;
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yugaayellow <=8'd5;
agreen <=8'd40;
aleft <=8'd15;
bred <=8'd65;
byellow <=8'd5;
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bleft <=8'd15;
bgreen <=8'd30;
end
assign acount=numa;
assign bcount=numb;
always@(podge clk) begin//交通灯a的控制
if(en)
bhdif(!tempa) begin
tempa<=1;
ca(counta)
0:begin numa<=agreen; lampa<=2; counta<=1;end 1:begin numa<=ayellow; lampa<=4; counta<=2;end 2:begin numa<=aleft; lampa<=1; counta<=3;end 3:begin numa<=ayellow; lampa<=4; counta<=4;end 4:begin numa<=ared; lampa<=8; counta<=0;end default:lampa<=8;
endca
end
el begin //倒计时,体会时序的实现方式
if(numa>0)
if(numa[3:0]==0) begin numa[3:0]<=4'b1001;numa[7:4]<=numa[7:4]-1;end
el numa[3:0]<=numa[3:0]-1;
if(numa==2) tempa<=0;cj lion
end
el begin counta<=0;tempa<=0;lampa<=4'b1000;end
end
always@(podge clk) begin//交通灯b的控制
if(en)
if(!tempb) begin
tempb<=1;
ca(countb)
0:begin numb<=bred; lampb<=8; countb<=1;end
1:begin numb<=bgreen; lampb<=2; countb<=2;end
2:begin numb<=byellow; lampb<=4; countb<=3;end
3:begin numb<=bleft; lampb<=1; countb<=4;end
4:begin numb<=byellow; lampb<=4; countb<=0;end
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endca
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el begin //倒计时,体会时序的实现方式
if(numb>0)
if(numb[3:0]==0) begin numb[3:0]<=4'b1001;numb[7:4]<=numb[7:4]-1;end
el numb[3:0]<=numb[3:0]-1;
if(numb==2) tempb<=0;
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el begin countb<=0;tempb<=0;lampb<=4'b1000;end
end
endmodule

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