Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. rerve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, plea contact the SAMSUNG branch office near you.
Revision No.0.01.0
2.0
2.12.22.32.4
2.5
Remark
Advance Preliminary
Preliminary
Preliminary
History
Initial issue.
1.Pin assignment of TBGA dummy ball is changed.(before) DNU --> (after) N.C
2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 36)
3. Add the data protection Vcc guidence for 1.8V device - below about 1.1V. (Page 37)
4. Add the specification of Block Lock scheme.(Page 32~35)
5. Pin assignment of TBGA A3 ball is changed.(before) N.C --> (after) Vss
6. Pin assignment of WSOP #38 pin is changed.(before) LOCKPRE --> (after) N.C
1. The Maximum operating current is changed.Program : Icc2 20mA-->25mA Era : Icc3 20mA-->25mA
The min. Vcc value 1.8V devices is changed.
K9F56XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V Pb-free Package is added.K9F5608U0C-FCB0,FIB0K9F5608Q0C-HCB0,HIB0K9F5616U0C-HCB0,HIB0K9F5616U0C-PCB0,PIB0
K9F5616Q0C-HCB0,HIB0 K9F5608U0C-HCB0,HIB0K9F5608U0C-PCB0,PIB0
Errata is added.(Front Page)-K9F56XXQ0C
tWC tWH tWP tRC tREH tRP tREA tCEA Specification 45 15 25 50 15 25 30 45Relaxed value 60 20 40 60 20 40 40 55
New definition of the number of invalid blocks is added.
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.)
1. The guidence of LOCKPRE pin usage is changed.
Don’t leave it N.C. Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss.(Before)
--> Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it N.C(After)2. 2.65V device is added.3.Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.)
Draft Date
大学英语四级听力下载Apr. 25th 2002Dec.14th 2002
Jan. 17th 2003
Mar. 5th 2003Mar. 13rd 2003
Mar. 26th 2003scored
Apr. 4th 2003Jun. 30th 2003
Note : For more detailed features and specifications including FAQ, plea refer to Samsung’s Flash
web site. /Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. rerve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, plea contact the SAMSUNG branch office near you.
Revision No.2.6
2.7
2.8
2.9
3.03.1
3.23.3marketplace
Remark
History
1. tREA value of 1.8V device is changed. K9F56XXQ0C : tREA 30ns --> 35ns
2. Errata is deleted.
1. AC parameters are changed.
tWC tWH tWP tRC tREH tRP tREA tCEA K9F56XXU0C
K9F56XXD0C 50 15 25 50 15 25 30 45 K9F56XXQ0C 60 20 40 60 20 40 40 55
1. AC parameters are changed.
tWC tWH tWP tRC tREH tRP tREA tCEA K9F5608Q0C 50 15 25 50 15 25 35 45 K9F5616Q0C 60 20 40 60 20 40 40 55
如何学好英语1. The Test Condition for Stand-by Currents are changed.
I SB 1: CE=V IH , WP=0V/V CC -->> CE=V IH , WP=LOCKPRE=0V/V CC
I SB 2: CE=V CC -0.2, WP=0V/V CC -->> CE=V CC -0.2, WP=LOCKPRE=0V/V CC 2. Add the Protrusion/Burr value in WSOP1 PKG Diagram .
1. PKG(TSOP1, WSOP1) Dimension Change 1. NAND Flash Technical Notes is changed.
-Invalid block -> initial invalid block ( page 16 ) -Error in write or read operation ( page 17 ) -Program Flow Chart ( page 17 )2. Package: TBGA->FBGA
1. Icc 15mA -> 20mA for 1.8V device
1. The flow chart to creat the initial invalid block is changed.
Draft Date
Aug. 18th 2003
Oct. 28th 2003
Dec. 17th 2003
Apr. 24th 2004
May. 24th 2004Oct. 25th. 2004
Apr. 22nd. 2005May 6th 2005
Note : For more detailed features and specifications including FAQ, plea refer to Samsung’s Flash web site. /Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
GENERAL DESCRIPTION
FEATURES
• Voltage Supply
- 1.8V device(K9F56XXQ0C) : 1.70~1.95V - 2.65V device(K9F56XXD0C) : 2.4~2.9V - 3.3V device(K9F56XXU0C) : 2.7 ~ 3.6 V • Organization
- Memory Cell Array
- X8 device(K9F5608X0C) : (32M + 1024K)bit x 8 bit - X16 device(K9F5616X0C) : (16M + 512K)bit x 16bit - Data Register
- X8 device(K9F5608X0C) : (512 + 16)bit x 8bit - X16 device(K9F5616X0C) : (256 + 8)bit x16bit • Automatic Program and Era - Page Program
- X8 device(K9F5608X0C) : (512 + 16)Byte - X16 device(K9F5616X0C) : (256 + 8)Word - Block Era :
bpr- X8 device(K9F5608X0C) : (16K + 512)Byte - X16 device(K9F5616X0C) : ( 8K + 256)Word • Page Read Operation - Page Size
- X8 device(K9F5608X0C) : (512 + 16)Byte - X16 device(K9F5616X0C) : (256 + 8)Word - Random Access : 10µs(Max.) - Serial Page Access : 50ns(Min.)* *K9F5616Q0C : 60ns • Fast Write Cycle Time
- Program time : 200µs(Typ.) - Block Era Time : 2ms(Typ.)
32M x 8 Bit / 16M x 16 Bit NAND Flash Memory
• Command/Address/Data Multiplexed I/O Port • Hardware Data Protection
- Program/Era Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Era Cycles - Data Retention : 10 Years • Command Register Operation • Intelligent Copy-Back
• Unique ID for Copyright Protection • Power-On Auto-Read Operation • Safe Lock Mechanism • Package
- K9F56XXX0C-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9F56XXX0C-GCB0/GIB0
63- Ball FBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm) - K9F5608U0C-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm) - K9F56XXX0C-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package - K9F56XXX0C-JCB0/JIB0
63- Ball FBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm) - Pb-free Package
- K9F5608U0C-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * K9F5608U0C-V,F(WSOPI ) is the same device as K9F5608U0C-Y ,P(TSOP1) except package type.
Offered in 32Mx8bit or 16Mx16bit, the K9F56XXX0C is 256M bit with spare 8M bit capacity. The device is offered in 1.8V, 2.65V, 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200µs on a 528-byte(X8 device) or 264-word(X16 device) page and an era operation can be performed in typ-ical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns(K9F5616Q0C : 60ns) cycle time per word. The I/O pins rve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and era functions including pul repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F56XXX0C ′s extended reliability of 100K program/era cycles by providing ECC(Error Correcting Code) with real
time mapping-out algorithm.
The K9F56XXX0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
PRODUCT LIST
Part Number Vcc Range Organization
PKG Type K9F5608Q0C-G,J 1.70 ~ 1.95V
X8FBGA K9F5616Q0C-G,J X16K9F5608D0C-Y ,P 2.4 ~ 2.9V
X8
TSOP1K9F5608D0C-G,J FBGA K9F5616D0C-Y ,P X16
TSOP1K9F5616D0C-G,J FBGA K9F5608U0C-Y ,P 2.7 ~ 3.6V
X8
TSOP1K9F5608U0C-G,J FBGA K9F5608U0C-V,F WSOP1K9F5616U0C-Y ,P X16TSOP1K9F5616U0C-G,J
FBGA
PIN CONFIGURATION (TSOP1)
K9F56XXU0C-YCB0,PCB0/YIB0,PIB0
N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C
Vss I/O15I/O7I/O14I/O6I/O13I/O5I/O12I/O4N.C
LOCKPRE Vcc N.C N.C N.C I/O11I/O3I/O10I/O2I/O9I/O1I/O8I/O0Vss
123456789101112131415161718192021222324
484746454443424140393837363534333231302928272625
N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.
C N.C
N.C N.C N.C N.C I/O7I/O6I/O5I/O4N.C N.C
LOCKPRE Vcc Vss N.C N.C N.C I/O3I/O2I/O1I/O0N.C N.C N.C N.C
X8
X16
X16
X8
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)48 - TSOP1 - 1220F
Unit :mm/Inch
0.787±0.008
20.00±0.20#1
#24
0.16+0.07
-0.03
0.008+0.003
-0.001
0.500.0197
#48
#25
0.48812.40M A X
12.000.472
0.10 0.004
M A X 0.250.010
()0.039±0.002
1.00±0.050.0020.05
MIN
0.0471.20
MAX
0.45~0.750.018~0.0300.724±0.004
18.40±0.100~8°
0.0100.25T Y Pggs
0.125+0.075
0.035
0.005+0.003
-0.001
0.500.020
()0.20+0.07
-0.03
63-Ball FBGA (measured in millimeters)
PACKAGE DIMENSIONS
9.00±0.10
#A1
Side View
Top View
1.00(M a x .)
0.45±0.05
4
321
A B
C D G Bottom View
11.00±0.10
63-∅0.45±0.05
0.80 x 7= 5.60
11.00±0.10
0.80 x 5= 4.00
0.800.25(M i n .)
0.10MAX
B
A
2.80
9.00±0.10
(Datum B)
(Datum A)
0.20 M A B
∅0.80
0.80 x 11= 8.80
0.80 x 9= 7.20 6
59.00±0.10
E
F H
K9F56XXX0C-GCB0,JCB0/GIB0,JIB0
R/B /WE /CE Vss ALE /WP /RE CLE NC NC NC
NC
Vcc NC NC I/O0I/O1NC NC
VccQ I/O5
I/O7Vss
I/O6
bronchitisI/O4
I/O3I/O2
Vss
NC
rearNC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
LOCKPRE NC NC
N.C
N.C N.C N.C N.C N.C
iouN.C
N.C
N.C N.C N.C N.C
N.C N.C
N.C N.C
N.C N.C N.C N.C N.C
N.C
N.C
N.C N.C N.C N.C
N.C N.C N.C R/B /WE /CE
Vss
ALE /WP /RE CLE I/O7
I/O5
I/O12IO14
Vcc
I/O10I/O8I/O1I/O9I/O0I/O3VccQ I/O6I/O15Vss
I/O13I/O4I/O11I/O2Vss
NC NC
NC NC
NC
NC NC NC NC NC
NC NC NC NC NC NC NC
LOCKPRE NC NC
X16
X8
3456
1 2
A B C
D G
E F
H
34
5
6
1 2
A B C
D G
E
F H
Top View
Top View
PIN CONFIGURATION (FBGA)
bed
2.00
PIN CONFIGURATION (WSOP1)
K9F5608U0C-VCB0,FCB0/VIB0,FIB0
123456789101112131415161718192021222324
484746454443424140393837363534333231302928272625
N.C N.C DNU N.C N.C N.C R/B RE CE DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.C
N.C N.C DNU N.C I/O7I/O6I/O5I/O4N.C DNU N.C Vcc Vss N.C DNU N.C I/O3I/O2I/O1I/O0N.C DNU N.C N.C
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)48 - WSOP1 - 1217F
Unit :mm
15.40±0.10
#1
#240.20
+0.07-0.03
0.16
+0.07-0.03
0.50T Y P (0.50±0.06)
#48
#25
0.10+0.075-0.035
17.00±0.20
0°~
8°
0.45~0.75
12.00±0.10
0.58±0.04
0.70 MAX
(0.01Min)
12.40MAX
