UC2526UC3526
DESCRIPTION
The UC1526 is a high performance monolithic pul width modulator circuit designed for fixed-frequency switching regulators and other power control applications. Included in an 18-pin dual-in-line pack-age are a temperature compensated voltage reference, sawtooth os-cillator, error amplifier, pul width modulator, pul metering and tting logic, and two low impedance power drivers. Also included are protective features such as soft-start and under-voltage lockout,digital current limiting, double pul inhibit, a data latch for single pul metering, adjustable deadtime, and provision for symmetry cor-rection inputs. For ea of interface, all digital control ports are TTL and B-ries CMOS compatible. Active LOW logic design allows wired-OR connections for maximum flexibility. This versatile device can be ud to implement single-ended or push-pull switching regu-lators of either polarity, both transformerless and transformer cou-pled. The UC1526 is characterized for operation over the full military temperature range of -55°C to +125°C. The UC2526 is characterized for operation from -25°C to +85°C, and the UC3526 is characterized for operation from 0° to +70°C.
Regulating Pul Width Modulator
FEATURES
bon•8 To 35V Operation
•5V Reference Trimmed To ±1%•1Hz To 400kHz Oscillator Range •Dual 100mA Source/Sink Outputs •Digital Current Limiting •Double Pul Suppression •Programmable Deadtime •Under-Voltage Lockout •Single Pul Metering •Programmable Soft-Start
•Wide Current Limit Common Mode Range •TTL/CMOS Compatible Logic Ports •Symmetry Correction Capability •
Guaranteed 6 Unit Synchronization
ABSOLUTE MAXIMUM RATINGS (Note 1, 2)
Input Voltage (+V IN ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V Collector Supply Voltage (+V C ). . .
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. . . . . . . . . . . . . . . . . . +40V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +V IN Source/Sink Load Current (each output). . . . . . . . . . . . . 200mA Reference Load Current. . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Logic Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Power Dissipation at T A = +25°C (Note 2). . . . . . . . . . 1000mW Power Dissipation at T C = +25°C (Note 2). . . . . . . . . . 3000mW Operating Junction Temperature . . . . . . . . . . . . . . . . . . +150°C Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (soldering, 10 conds). . . . . . . . . . +300°C Note 1:Values beyond which damage may occur.baru
Note 2:Consult packaging ction of databook for thermal
limitations and considerations of package.
RECOMMENDED OPERATING CONDITIONS (Note 3)
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8V to +35V Collector Supply Voltage . . . . . . . . . . . . . . . . . . . +4.5V to +35V Sink/Source Load Current (each output). . . . . . . . . 0 to 100mA Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA Oscillator Frequency Range . . . . . . . . . . . . . . . . 1Hz to 400kHz Oscillator Timing Resistor . . . . . . . . . . . . . . . . . . . 2k Ω to 150k ΩOscillato
complimentr Timing Capacitor . . . . . . . . . . . . . . . . . . . 1nF to 20µF Available Deadtime Range at 40kHz. . . . . . . . . . . . . 3% to 50%Operating Ambient Temperature Range
UC1526. . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C UC2526 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C UC3526. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0°C to +70°C Note 3:Range over which the device is functional and
parameter limits are guaranteed.
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ELECTRICAL CHARACTERISTICS:Note 4: I L = 0mA.
+V IN = 15V, and over operating ambient temperature, unless otherwi
specified, T A = T J.
ELECTRICAL CHARACTERISTICS:
+V IN = 15V, and over operating ambient temperature, unless otherwi
specified, T A = T J.
Note 4: I L = 0mA.Note 5: F OSC = 40kHz (R T = 4.12k Ω ± 1%, C T = 0.1µF ± 1%,
R D = 0Ω)Note 6: V CM = 0 to +5.2V Note 8: V C = +15V Note 9: +V IN = +35V, R T = 4.12k Ω
APPLICATIONS INFORMATION
Voltage Reference
T he reference regulator of the UC1526 is bad on a tem-
perature compensated zener diode. The circuitry is fully active at supply voltages above +8V, and pr
ovides up to 20mA of load current to external circuitry at +5.0V. In sys-tems where additional current is required, an external PNP transistor can be ud to boost the available current.A rugged low frequency audio-type transistor s hould be ud, and lead lengths between the PWM and transistor should be as short as possible to minimize the risk of os-cillations. Even so, some types of transistors may require collector-ba capacitance for stability. Up to 1 amp of load current can be obtained with excellent regulation if the device lected maintains high current gain.
darling的意思Under-Voltage Lockout
The under-voltage lockout circuit protects the UC1526and the power devices it controls from inadequate supply voltage, If +V IN is too low, the circuit disables the output drivers and holds the RESET _______
pin LOW. This prevents spurious output puls while the control circuitry is stabi-lizing, and holds the soft-start timing capacitor in a dis-charged state.
The circuit consists of a +1.2V bandgap reference and comparator circuit which is active when the reference voltage has rin to 3V BE or +1.8V at 25°C. When the ref-erence voltage ris to approximately +4.4V, the circuit enables the output drivers and releas the RESET _______ pin,allowing a normal soft-start. The comparator has 200mV of hysteresis to minimize oscillation at the trip point.When +V IN to the PWM is removed and the reference drops to +4.2V, the under-voltage circuit pulls RESET _______LOW again. The soft-start capacitor is immediately dis-charged,
and the PWM is ready for another soft-start cy-cle.
The UC1526 can operate from a +5V supply by connect-ing the V REF pin to the +V IN pin and maintaining the sup-ply between +4.8 and +5.2V.
Soft-Start Circuit
The soft-start circuit protects the power transistors and rectifier diodes from high current surges during power supply turn-on. When supply voltage is first applied to the UC1526, the under-voltage lockout circuit holds RESET _______LOW with Q 3. Q 1 is turned on, which holds the soft-start capacitor voltage at zero. The cond collector of Q 1clamps the output of the error amplifier to ground, guaran-teeing zero duty cycle at the driver outputs. When the supply voltage reaches normal operating range, RESET _______will go HIGH. Q 1 turns off, allowing the internal 100mA current source to charge C S . Q 2 clamps the error ampli-fier output to 1V BE above the voltage on C S . As the soft-start voltage ramps up to +5V, the duty cycle of the PWM linearly increas to whatever value the voltage regula-tion loop requires for an error null.
剑桥少儿英语教材Digital Control Ports
The three digital control ports of the UC1526 are bi-direc-tional. Each pin can drive TTL and 5V CMOS logic di-rectly, up to a fan-out of 10 low-power Schottky gates.
Each pin can also be directly driven by open-collector Under-Voltage Lockout Schematic
farmerExtending Reference Output Current
TTL, open-drain CMOS, and open-collector voltage com-parators; fan-in is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin is pulled LOW to activate the particular function. Driving SYNC ______
LOW in-itiates a discharge cycle in the oscillator. Pulling SHUTDOWN ____________
LOW immediately inhibits all PWM output puls. Holding RESET _______
LOW discharges the soft-start capacitor. The logic threshold is +1.1V at +25°C. Noi immunity can be gained at the expen of fan-out with an external 2k pull-up resistor to +5V.
Oscillator
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The oscillator is programmed for frequency and dead time with three components: R T , C T and R D . Two waveforms are generated: a sawtooth waveform at pin 10 for pul width modulation, and a logic clock at pin 12. The follow-ing procedure is recommended for choosing timing val-ues:
1. With R D = 0 (pin 11 shorted to ground) lect values for R T and C T from Figure 7 to give the desired oscillator period. Remember that the frequency at each driver out-put is half the oscillator frequency, and the frequency at the +V C terminal is the same as the oscillator frequency.
2. If more dead time is required, lect a large value of R D . At 40kHz dead time increas by 400ns/Ω .英语四级考试作文
3. Increasing the dead time will cau the oscillator fre-quency to decrea slightly. Go back and decrea the value of R T slightly to bring the frequency back to the nominal design value.
The UC1526 can be synchronized to an external logic clock by programming the oscillator to free-run at a fre-quency 10% slower than the sync frequency. A periodic LOW logic pul approximately 0.5µs wide at the SYNC ______pin will then lock the oscillator to the external frequency.
Multiple devices can be synchronized together by pro-gramming one master unit for the desired freq
uency and then sharing its sawtooth and clock waveforms with the slave units. All C T terminals are connected to the C T pin of the master, and all SYNC ______ terminals are likewi con-nected to the SYNC ______
pin of the master. Slave R T termi-nals are left open or connected to V REF . Slave R D terminals may be either left open or grounded.Error Amplifier
The error amplifier is a transconductance design, with an output impedance of 2M Ω . Since all voltage gain takes place at the output pin, the open-loop gain/frequency characteristics can be controlled with shunt reactance to ground. When compensated for unity-gain stability with 100pF , the amplifier has an open-loop pole at 800Hz.The input connections to the error amplifier are deter-mined by the polarity of the switching supply output volt-age. For positive supplies, the common-mode voltage is +5.0V and the feedback connections in Figure 6A are ud. With negative supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the +5.0V reference voltage, as shown in Figure 6B.Output Drivers
The totem-pole output drivers of the UC1526 are de-signed to source and sink 100mA continuously and 200mA peak. Loads can be driven either from the output pins 13 and 16, or from the +V C , as required.
Since the bottom transistor of the totem-pole is allowed to saturate, there is a momentary conduction path from the +V C terminal to ground during switching. T o limit the re-sulting current spikes a small resistor in ries with pin 14is always recommended. The resistor value is deter-mined by the driver supply voltage, and should be chon for 200mA peak currents.
UC3526
Figure 5. Oscillator Connections and Waveforms
Digital Control Port Schematic APPLICATIONS INFORMATION (cont.)
UC3526
