NCP4330
Post Regulation Driver中译英在线翻译器
The NCP4330 hous a dual MOSFET driver intended to be ud as a companion chip in AC−DC or DC−DC multi−output post regulated power supplies. Being directly fed by the condary AC signal, the device keeps power dissipation to the lowest while reducing the surrounding part count. Furthermore, the implementation of a N−channel MOSFET gives NCP4330−bad applications a significant advantage in terms of efficiency.
Features
•Undervoltage Lockout
•Thermal Shutdown for Overtemperature Protection
•PWM Operation Synchronized to the Converter Frequency •High Gate Drive Capability
•Bootstrap for N−MOSFET High−Side Drive •Over−Lap Management for Soft Switching •High Efficiency Post−Regulation •Ideal for Frequencies up to 400 kHz •
This is a Pb−Free Device
Typical Applications
•ATX 3V3 Post−Regulation
•Offline SMPS with MAGAMP Post−Regulation •Multi−Outputs DC−DC Converters
花仙子歌词Figure 1. Block Diagram
V
1ORDERING INFORMATION
Device Package Shipping †NCP4330DR2G
SO−8(Pb−Free)
2500 / Tape & Reel
HS_DRV GND BST RST C_ramp LS_DRV V DD I_ramp
(Top View)
MARKING DIAGRAM
SO−8D SUFFIX CASE 751
4330D = Device Number A = Asmbly Location L = Wafer Lot Y = Year
剑桥英语预备级W
= Work Week
PIN CONNECTIONS
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†For information on tape and reel specifications,including part orientation and tape sizes, plea refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Figure 2. Timing Diagram(s)
Converter Winding
Voltage
C_ramp Voltage
High−Side Driver Low−Side Driver
(referenced to
HS MOSFET source)
Synchronization
Signal
Internal RESET
Signal DETAILED PIN DESCRIPTION(S)
Pin Number
Name Function
1HS_DRV “HS_DRV” is the gate driver of the high−side MOSFET.
2
BST
“BST” is the bootstrap pin. A 0.1 m F to 1.0 m F ceramic capacitor should be connected between this pin and the node that is common to the coil and the two MOSFET. The “BST” voltage feeds the high−side driver (“HS_DRV”).occupation是什么意思
3RST The “RST” pin rets the C_ramp voltage in order to synchronize the post−regulator free−wheeling quence to the forward converter demagnetization pha.
4C_ramp The capacitor connected to the C_ramp pin enables to adjust the delay in turning on the high−side MOSFET (in conjunction with “I_ramp” current).
5
I_ramp
The “I_ramp” pin receives a current supplied by a regulation means. This current adjusts the delay after which the high−side MOSFET is turned on. By this way, it modules the high−side MOSFET on time in order to regulate the output voltage.
6V DD “V DD ” is the power supply input. A 0.1 m F to 1.0 m F ceramic capacitor should be connected from this pin to ground for decoupling.
7LS_DRV “LS_DRV” is the driver output of the low−side MOSFET gate.8
GND
克里斯汀娜
Ground.
MAXIMUM RATINGS
Symbol Rating Value Unit BST Bootstrap Input−0.3, +40V RST Ret Input−0.3, +5.0V C_ramp Timing Capacitor Node (Note 1)−0.3, V rampHL V I_ramp Regulation Current Input (Note 1)−0.3, Vcl V V DD Supply Voltage−0.3, +20V R q JA Thermal Resistance180°C/W T J Operating Junction Temperature Range (Note 2)−40, +125°C T Jmax Maximum Junction Temperature150°C T Smax Storage Temperature Range−65 to +150°C T Lmax Lead Temperature (Soldering, 10 s)300°C Maximum ratings are tho values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If the limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
1.V rampHL and Vcl are the internal clamp levels of pins 4 and 5 respectively.
2.The maximum junction temperature should not be exceeded.
ELECTRICAL CHARACTERISTICS (V DD = 10 V, V BST= 25 V, T J from −25°C to +125°C, unless otherwi specified.)
Symbol Characteristic Min Typ Max Unit High−Side Output Stage
V HS_H High−Side Output Voltage in High State @ Isource = −100 mA22.523.5−V V HS_L High−Side Output Voltage in Low State @ Isink = 100 mA−0.9 1.5V
I source_HS Current Capability of the High−Side Drive Output in High State−0.5−A
I sink_HS Current Capability of the High−Side Drive Output in Low State−0.75−A
t r−HS High−Side Output Voltage Ri Time from 0.5 V to 12 V (C L= 1.0 nF)−25−ns t f−HS High−Side Output Voltage Fall Time from 20 V to 0.5 V (C L= 1.0 nF)−25−ns T LS−HS Delay from Low−Side Gate Drive Low (High) to High−Side Drive High (Low)−100−ns Low−Side Output Stage
V LS_H Low−Side Output Voltage in High State @ Isource = −500 mA7.48.2−V V LS_L Low−Side Output Voltage in Low State @ Isink = 750 mA− 1.3 1.7V
I source_LS Current Capability of the Low−Side Drive Output in High State−0.5−A
I sink_LS Current Capability of the Low−Side Drive Output in Low State−0.75−A
t r−LS Low−Side Output Voltage Ri Time from 0.5 V to 7.0 V (C L= 2.0 nF)−25−ns t f−LS Low−Side Output Voltage Fall Time from 9.5 V to 0.5 V (C L= 2.0 nF)−25−ns Ramp Control
I charge C_ramp Current
@ Ipin5 = 100 m A @ Ipin5 = 1.5 mA
90
1400
102
1590
110
1800
m A
Vcl Pin5 Clamp Voltage @ Ipin5 = 1.5 mA0.7 1.4 2.1V Vref L Ramp Control Reference Voltage, Vpin4 Falling 1.3 1. 5 1.7V Vref H Ramp Control Reference Voltage, Vpin4 Rising 2.25 2.5 2.75V V rampHL Ramp Voltage Maximum Value @ Ipin5 = 1.5 mA 3.2 3.6 4.2V V rampLL Ramp Voltage Low Voltage @ Ipin5 = 1.5 mA−−100mV
ELECTRICAL CHARACTERISTICS (continued) (V DD = 10 V, V BST= 25 V, T J from −25°C to +125°C, unless otherwi specified.)
Symbol Characteristic Min Typ Max Unit V DD Management
UVD H Undervoltage Lockout Threshold (V DD Rising) 5.2 5.8 6.4V UVD L Undervoltage Lockout Threshold (V DD Falling) 4.9 5.2 5.5V
H UVD Undervoltage Lockout Hysteresis400600−mV
I DD1 I DD2 I DD3Consumption:
@ Vpin4 = 3.0 V and Ipin5 = 500 m A
@ Vpin4 = 0 V and Ipin5 = 500 m A
@ Vpin4 Oscillating 0 to 3.0 V at 200 kHz, Ipin5 = 500 m A
−
−
−
13
7.0
10
20
12
15
mA
Ret Block
V rst_th Ret Block Threshold 2.2 2.5 2.8V
H rst Ret Comparator Hysteresis0.8 1.0−V
T ret Ret Pul Duration−250500ns
I ret C_ramp Pin Average Current, a 200 kHz, 50% duty cycle Pul Generator
being applied to ret pin and 1.0 V to pin 4 (C_ramp) and @ Iramp = 0
0.30.7−mA V cl−neg Negative Clamp Level @ Ipin3 = −2.0 mA−0.5−0.30V Temperature Protection
T limit Thermal Shutdown Threshold−150−°C
H temp Thermal Shutdown Hysteresis−50−°C
−25
1825
I D D 1 (m A )
8Figure 3. I DD1 Consumption
vs. Temperature Figure 4. I DD2 Consumption
vs. Temperature
Figure 5. I DD3 Consumption
vs. Temperature Figure 6. Undervoltage Lockout Upper
Threshold vs. Temperature
Figure 7. Undervoltage Lockout Lower
Threshold vs. Temperature TEMPERATURE (°C)
1014
16125
Figure 8. Undervoltage Lockout Hysteresis
vs. Temperature
12
−25
9.025
I D D 2 (m A )
5.0TEMPERATURE (°C)
5.87.4
8.2125
6.6
−25
1425
I D D 3 (m A )
8TEMPERATURE (°C)macropus
101213125
11−25
6.025
U V D _H (V ) 5.5TEMPERATURE (°C)
5.65.8
5.9125
5.7
9−25
高中短文改错
70025
H _U V D (V )
460TEMPERATURE (°C)
500
580620125
540
−25
25
U V D _L (V )
5.14
TEMPERATURE (°C)
5.16
5.20
5.22125
5.18
660
−25
10825
I p i n 4 (m A )
96Figure 9. Pin4 Charge Current vs. Temperature
(@ Ipin5 = 100 m A)Figure 10. Pin4 Charge Current vs. Temperature
(@ Ipin5 = 1.5 mA)
Figure 11. Pin5 Clamp Voltage vs. Temperature Figure 12. Pin4 Clamp Voltage vs. Temperature
Figure 13. Ramp Control Reference Voltage vs.
Temperature (Vpin4 falling)TEMPERATURE (°C)
98102104125Figure 14. Ramp Control Reference Voltagei wanna be free
vs. Temperature (Vpin4 rising)
100−25170025
I p i n 4 (m A )
1500
TEMPERATURE (°C)
154016201660
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125
1580
−25
25
V c l (V )
0.8TEMPERATURE (°C)
1.2
1.61.8125
1.4
−25
3.7525
V r a m p H L (V )
3.45
TEMPERATURE (°C)
3.503.603.65125
3.551.0
−25
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V r e f L (V )
1.50
TEMPERATURE (°C)
1.521.561.60125
1.54
106 3.701.58−25
25
V r e f H (V )
2.50
TEMPERATURE (°C)
2.522.56
2.60
125
2.54
2.58
