CMOS 300 MSPS Complete DDS
AD9852 Rev. E
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responsibility is assumed by Analog Devices for its u, nor for any infringements of patents or other rights of third parties that may result from its u. Specifications subject to change without notice. No licen is granted by implication or otherwi under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights rerved.
语文表达方式有哪些FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit D/A converters
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) A OUT
4× to 20× programmable reference clock multiplier Dual 48-bit programmable frequency registers
crowds
Dual 14-bit programmable pha offt registers
12-bit programmable amplitude modulation and on/off output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via I/O interface
Linear or nonlinear FM chirp functions with single pin frequency hold function Frequency ramped FSK
<25 ps rms total jitter in clock generator mode Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interface
10 MHz rial 2-wire or 3-wire SPI-compatible
100 MHz parallel 8-bit programming
3.3 V single supply
answers
Multiple power-down functions
Single-ended or differential input reference clock Small, 80-lead LQFP or TQFP with expod pad APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems Test and measurement equipment
rip是什么梗Commercial and amateur RF exciter
FUNCTIONAL BLOCK DIAGRAM
SET
guildhallPARALLEL SELECT
OR SERIAL
PROGRAMMING
LINES
PARALLEL
LOAD
RESET
困境英语
S
6
belin
3
4
-
1
Figure 1.
AD9852
Rev. E | Page 2 of 52
TABLE OF CONTENTS
<1 Functional 1 .3 5 Absolute 8 8 Explanation of 8 8 Pin Configuration and 9 Typical 12 T
16 Modes 18 Single Tone (Mode 000).............................................................18 Unramped FSK (Mode 001)......................................................19 Ramped FSK (Mode 010)..........................................................19 Chirp (Mode 011).......................................................................22 BPSK (Mode 100).......................................................................26 Using 27 Internal and External 27 On/Off Output Shaped Keying (OSK)....................................27 29 Control DAC. (29)
benchmark是什么意思Inver 29 29 High .30 Programming 31 .31 Parallel I/
.........................31 Serial Port I/.31 General Operation of the 34 34 Serial Interface Port .35 MSB/35 Control 36 Power Dissipation and .38 38 Junction 38 Evaluation of .40 Thermally Enhanced Package 40 41 Evaluation 41 General 41 Using the 43 51 Ordering Guide.. (52)
AD9852
Rev. E | Page 3 of 52
REVISION HISTORY
5/07—Rev. D to Rev. E
Changed AD9852ASQ .Universal Changed AD9852AST Universal Change 1 Changes to Endnote 10 of .7 Changes to Absolute 8 Added Thermal 8 Change to Ramped FSK (Mode 010) .19 Change to Internal and External Update 27 Change to Thermal 38 Changes to Junction Temperature 38 Changes to Thermally Enhanced Package Mounting
40 Deleted Figure 61 to 41 Changes to .44 Updated
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......................51 Changes to 52 12/05—Rev. C to Rev. D
Universal Changes to 4 Changes to Explanation of Test 9 Change to 10 Changes to 47 Changes to .52 Changes to 52 4/04—Rev. B to Rev. C
Universal Changes to 1 Changes to 3 Changes to 4 Changes to 6 Changes to 8 Changes to 17 Changes to Equation in Ramped FSK (Mode 010).....................19 Changes to Evaluation 39 Changes to
General Operating 39 Changes to Using the Provided .42 Changes to 43 Changes to 44 Changes to Figure 72 and 48 Changes to Ordering Guide.. (48)
3/02—Rev. A to Rev. B
Changes to 1 Changes to Functional 1 Changes 3 Changes to Absolute 5 Changes to Pin 6 Changes to 8 Deleted 11 Changes to Figure 18 and 11 Changes to BPDK 21 Changes to Differential Refclk 24 Changes to Master 24 Changes to Parallel I/O 24 Changes to General Operation of the Serial
27 Changes to 27 Changes to Figure 65. (36)
AD9852
Rev. E | Page 4 of 52
GENERAL DESCRIPTION
The AD9852 digital synthesizer is a highly integrated device that us advanced DDS technology, coupled with an internal high speed, high performance D/A converter to form a digitally programmable, agile synthesizer function. When referenced to an accurate clock source, the AD9852 generates a highly stable frequency-, pha-, and amplitude-programmable cosine output that can be ud as an agile LO in communications, radar, and many other applications. The innovative high speed DDS core of the AD9852 provides 48-bit frequency resolution (1 μHz tuning resolution with 300 MHz SYSCLK). Maintaining 17 bits ensures excellent SFDR.
The circuit architecture of the AD9852 allows the generation of output signals at frequencies up to 150 MHz, which can be digitally tuned at a rate of up to 100 million new frequencies per cond. The
(externally filtered) cosine wave output can be converted to a square wave by the internal comparator for agile clock generator applications. The device provides two 14-bit pha registers and a single pin for BPSK operation.
For higher-order PSK operation, the I/O interface can be ud for pha changes. The 12-bit cosine DAC, coupled with the innovative DDS architecture, provides excellent wideband and narrow-band output SFDR. When configured with the
comparator, the 12-bit control DAC facilitates static duty cycle control in the high speed clock generator applications. The 12-bit digital multiplier permits programmable amplitude modulation, on/off output shaped keying, and preci amplitude control of the cosine DAC output. Chirp functionality is also included for wide bandwidth frequency sweeping applications. The AD9852 programmable 4× to 20× REFCLK multiplier cir-cuit internally generates the 300 MHz system clock from a lower frequency external reference clock. This saves the ur the expen and difficulty of implementing a 300 MHz system clock source. Direct 300 MHz clocking is also accommodated with either single-ended or differential inputs. Single-pin, conventional FSK and the enhanced spectral qualities of ramped FSK are supported. The AD9852 us advanced 0.35 μ CMOS technology to provide this high level of functionality on a single 3.3 V supply.
The AD9852 is pin-for-pin compatible with the AD9854 single-tone synthesizer. The AD9852 is specified to operate over the extended industrial temperature range of −40°C to +85°C.
OVERVIEW
The AD9852 digital synthesizer is a highly flexible device that address a wide range of applications. The device consists of an NCO with a 48-bit pha accumulator, a programmable reference clock multiplier, an inver sinc filter, a digital multiplier, two 12-bit/300 MHz DACs, a high speed analog comparator, and an interface logic. This highly integrated device can be configured to rve as a synthesized LO agile clock generator and FSK/BPSK modulator. The theory of
operation for the functional blocks of the device and a technical description of the signal flow through a DDS device is provided by Analog Devices, Inc., in the tutorial A Technical Tutorial on Digital Signal Synthesis . The tutorial also provides basic applications information for a variety of digital synthesis implementations.
AD9852
Rev. E | Page 5 of 52
SPECIFICATIONS
V S = 3.3 V ± 5%, R SET = 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9852ASVZ, external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9852ASTZ, unless otherwi noted. Table 1.
Test AD9852ASVZ AD9852ASTZ Parameter Temp Level M in Typ M ax M in Typ M
ax Unit
REFERENCE CLOCK INPUT CHARACTERISTICS 1
Internal System Clock Frequency Range REFCLK Multiplier Enabled Full VI 20 300 20 200 MHz REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz External Reference Clock Frequency Range REFCLK Multiplier Enabled Full VI 5 75 5 50 MHz REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz Duty Cycle 25°C IV 45 50 55 45 50 55 % Input Capacitance 25°C IV 3 3 pF Input Impedance 25°C IV 100 100 kΩ Differential Common-Mode Voltage Range
Minimum Signal Amplitude 2
25°C IV 400 400 mV p-p Common-Mode Range 25°C IV 1.6 1.75 1.9 1.6 1.75 1.9 V V IH (Single-Ended Mode) 25°C IV 2.3 2.3 V V IL (Single-Ended Mode) 25°C IV 1 1 V DAC STATIC OUTPUT CHARACTERISTICS Output Update Speed Full I 300 200 MSPS Resolution 25°C IV 12 12 Bits Cosine and Control DAC Full-Scale Output Current 25°C IV 5 10 20 5 10 20 mA
Gain Error 25°C I −6 +2.25 −6 +2.2
2323
5
% FS Output Offt 25°C I 2 2 μA Differential Nonlinearity 25°C I 0.3 1.25 0.3 1.25 LSB Integral Nonlinearity 25°C I 0.6 1.66 0.6 1.66 LSB Output Impedance 25°C IV 100 100 kΩ Voltage Compliance Range 25°C I −0.5 +1.0 −0.5 +1.0 V DAC DYNAMIC OUTPUT CHARACTERISTICS DAC Wideband SFDR 1 MHz to 20 MHz A OUT 25°C V 58 58 dBc 20 MHz to 40 MHz A OUT 25°C V 56 56 dBc 40 MHz to 60 MHz A OUT 25°C V 52 52 dBc 60 MHz to 80 MHz A OUT 25°C V 48 48 dBc 80 MHz to 100 MHz A OUT 25°C V 48 48 dBc 100 MHz to 120 MHz A OUT 25°C V 48 dBc DAC Narrow-Band SFDR 10 MHz A OUT (±1 MHz) 25°C V 83 83 dBc 10 MHz A OUT (±250 kHz) 25°C V 83 83 dBc 10 MHz
A OUT (±50 kHz) 25°C V 91 91 dBc 41 MHz A OUT (±1 MHz) 25°C V 82 82 dBc 41 MHz A OUT (±250 kHz) 25°C V 84 84 dBc 41 MHz A OUT (±50 kHz) 25°C V 89 89 dBc 119 MHz A OUT (±1 MHz) 25°C V 71 dBc 119 MHz A OUT (±250 kHz) 25°C V 77 dBc 119 MHz A OUT (±50 kHz) 25°C V 83 dBc
AD9852
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Test AD9852ASVZ AD9852ASTZ Parameter Temp Level M in Typ M ax M in Typ M ax Unit Residual Pha Noi
(A OUT = 5 MHz, External Clock = 30 MHz,
REFCLK Multiplier Engaged at 10×) 1 kHz Offt 25°C V 140 140 dBc/Hz 10 kHz Offt 25°C V 138 138 dBc/Hz 100 kHz Offt 25°C V 142 142 dBc/Hz
(A OUT = 5 MHz, External Clock = 300 MHz,
REFCLK Multiplier Bypasd) 1 kHz Offt 25°C V 142 142 dBc/Hz 0 kHz Offt 25°C V 148 148 dBc/Hz 100 kHz Offt 25°C V 152 152 dBc/Hz
PIPELINE DELAYS 3, 4, 5
DDS Core (Pha Accumulator and
Pha-to-Amp Converter) 25°C IV 33 33 SYSCLK cycles Frequency Accumulator 25°C IV 26 26 SYSCLK cycles Inver Sinc Filter 25°C IV 16 16 SYSCLK cycles Digital Multiplier 25°C IV 9 9 SYSCLK cycles DAC 25°C IV 1 1 SYSCLK cycles I/O Update Clock (Internal Mode) 25°C IV 2 2 SYSCLK cycles I/O Update Clock (External Mode) 25°C IV 3 3 SYSCLK cycles MASTER RESET DURATION 25°C IV 10 10 SYSCLK cycles COMPARATOR INPUT CHARACTERISTICS Input Capacitance 25°C V 3 3 pF Input Resistance 25°C IV 500 500 kΩ Input Current 25°C I ± 1 ± 5 ± 1 ± 5 μA Hysteresis 25°C IV 10 20 10 20 mV p-p COMPARATOR OUTPUT CHARACTERISTICS Logic 1 Voltage, High-Z Load Full VI 3.1 3.1 V Logic 0 Voltage, High-Z Load Full VI 0.16 0.16 V
Output Power, 50 Ω Load, 120 MHz Toggle Rate 25°C I 9 11 9 11 dBm
Propagation Delay 25°C IV 3 3 ns
Output Duty Cycle Error 6
25°C I −10 ± 1 +10 −10 ± 1 +10 % Ri/Fall Time, 5 pF Load 25°C V 2 2 ns Toggle Rate, High-Z Load 25°C IV 300 350 300 350 MHz Toggle Rate, 50 Ω Load 25°C IV 375 400 375 400 MHz
Output Cycle-to-Cycle Jitter 7
25°C IV 4.0 4.0 ps rms COMPARATOR NARROW-BAND SFDR 8 10 MHz (±1 MHz) 25°C V 84 84 dBc 10 MHz (±250 MHz) 25°C V 84 84 dBc 10 MHz (±50 kHz) 25°C V 92 92 dBc 41 MHz (±1 MHz) 25°C V 76 76 dBc 41 MHz (±250 kHz) 25°C V 82 82 dBc 41 MHz (±50 kHz) 25°C V 89 89 dBc 119 MHz (±1 MHz) 25°C V 73 dBc 119 MHz (±250 kHz) 25°C V 73 dBc 119 MHz (±50 kHz) 25°C V 83 dBc CLOCK GENERATOR OUTPUT JITTER 8 5 MHz A OUT 25°C V 23 23 ps rms 40 MHz A OUT 25°C V 12 12 ps rms 100 MHz A OUT 25°C V 7 7 ps rms