michael phelps专利名称：Methods for using checksums in X-tolerant
test respon compaction in scan-bad
testing of integrated circuitsdictionaryentry
发明人：Mikhail I. Grinchuk,Ahmad A. Alyamani,Erikignore是什么意思
david beckham
Chmelar
申请号：US11131990
申请日：20050518
自学日语教材
公开号：US20060282728A1
公开日：
20061214
专利内容由知识产权出版社提供
anaconda
蛋糕制作培训专利附图：成都美视国际学校
摘要：Methods for designing and using checksums in X-tolerant test respon
compaction in scan-bad testing of integrated circuits. Flip-flops of a chip are treated as points of a discrete geometrical structure described in terms of points and lines (e.g., a two-dimensional structure, or the like). Each point reprents a MUXed flip-flop holding a value. Each line (with points on it) reprents a checksum: bit values of flip-flops corresponding to points on the line are all XORed together. A t of all checksums (“lines”) may be parated into subts, where each subt contains parallel lines. One of the subts (such that each point belongs to one of lines of the subt) reprents scan chains, each line reprenting one scan chain. In a preferred embodiment, a compactor contains parate parts for each of the subts such that complexity (the number of gates) of each part depends on the number of scan chains and does not depend on their lengths. Values of checksums may be ud as follows. If a checksum includes at least one X-bit, the checksum is deleted from the t of calculated checksums. The remaining checksums of the t of calculated checksums are compared with pre-computed values. If the remaining checksums and the pre-computed values fail to match, then the chip is identified as malfunctional.
申请人：Mikhail I. Grinchuk,Ahmad A. Alyamani,Erik Chmelar
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地址：San Jo CA US,Santa Clara CA US,San Jo CA US
国籍：US,US,US
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