General Description
The DS3231 is a low-cost, extremely accurate I 2C real-time clock (RTC) with an integrated temperature-compensated crystal oscillator (TCXO) and crystal. The device incorporates a battery input, and maintains accurate timekeeping when main power to the device is interrupted. The integration of the crystal resonator enhances the long-term accuracy of the device as well as reduces the piece-part count in a manufacturing line. The DS3231 is available in commercial and industrial temperature ranges, and is offered in a 16-pin, 300-mil SO package.
The RTC maintains conds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM /PM indicator. Two programmable time-of-day alarms and a programmable square-wave output are provided. Address and data are transferred rially through an I 2C bidirectional bus.
A precision temperature-compensated voltage reference and comparator circuit monitors the status of V CC to detect power failures, to provide a ret output, and to automatically switch to the backup supply when necessary. Additionally, the RST pin is monitored as a pushbutton input for generating a μP ret.
Benefits and Features
nfa●Highly Accurate RTC Completely Manages All
Timekeeping Functions
•Real-Time Clock Counts Seconds, Minutes, Hours,Date of the Month, Month, Day of the Week, and Year, with Leap-Year Compensation Valid Up to 2100•Accuracy ±2ppm from 0°C to +40°C •Accuracy ±3.5ppm from -40°C to +85°C •Digital Temp Sensor Output: ±3°C Accuracy •Register for Aging Trim
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•RST Output/Pushbutton Ret Debounce Input •Two Time-of-Day Alarms
•Programmable Square-Wave Output Signal ●Simple Serial Interface Connects to Most
Microcontrollers
•Fast (400kHz) I 2C Interface
●Battery-Backup Input for Continuous Timekeeping
•Low Power Operation Extends Battery-Backup Run Time
• 3.3V Operation ●Operating Temperature Ranges: Commercial
(0°C to +70°C) and Industrial (-40°C to +85°C)●Underwriters Laboratories ® (UL) Recognized Applications
Underwriters Laboratories is a registered certification mark of Underwriters Laboratories Inc.
Ordering Information and Pin Configuration appear at end of data sheet.
●Servers ●Telematics
●Utility Power Meters ●GPS
DS3231
Extremely Accurate I 2C-Integrated
RTC/TCXO/Crystal
to the DS3231 rets becau of a loss of V CC or other event, it is possible that the microcontroller and DS3231 I 2C communications could become unsynchronized, e.g., the microcontroller rets while reading data from the DS3231. When the microcontroller rets, the DS3231 I 2C interface may be placed into a known state by tog-gling SCL until SDA is obrved to be at a high level. At that point the microcontroller should pull SDA low while SCL is high, generating a START condition.
Clock and Calendar
The time and calendar information is obtained by reading the appropriate register bytes. Figure 1 illu
strates the RTC registers. The time and calendar data are t or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded
Note: Unless otherwi specified, the registers’ state is not defined when power is first applied.
hoistFigure 1. Timekeeping Registers
ADDRESS
BIT 7MSB BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0LSB
FUNCTION RANGE 00h 010 Seconds Seconds Seconds 00–5901h 010 Minutes Minutes
Minutes 00–5902h 012/24AM /PM 10 Hour
Hour
Hours
1–12 + AM /PM
00–23
20 Hour
03h 000
Day
Day 1–704h 0010 Date
Date Date 01–3105h Century
10 Month
Month Month/Century 01–12 + Century
06h 10 Year
Year Year 00–9907h A1M110 Seconds Seconds Alarm 1 Seconds 00–5908h A1M210 Minutes Minutes Alarm 1 Minutes 00–5909h A1M312/24AM /PM 10 Hour
Hour Alarm 1 Hours 1–12 + AM /PM
00–23
20 Hour
0Ah A1M4DY/DT
certified10 Date
Day Alarm 1 Day 1–7Date Alarm 1 Date 1–310Bh A2M210 Minutes Minutes
Alarm 2 Minutes 00–590Ch A2M312/24AM /PM 10 Hour
Hour Alarm 2 Hours 1–12 + AM /PM
00–23
20 Hour
0Dh A2M4DY/DT 10 Date Day Alarm 2 Day 1–7Date
Alarm 2 Date 1–310Eh EOSC BBSQW
CONV RS2
中专升本科
RS1INTCN A2IE A1IE Control —0Fh OSF 000EN32kHz BSY A2F A1F Control/Status —10h SIGN DATA DATA DATA DATA DATA DATA DATA Aging Offt —11h SIGN DATA DATA DATA DATA DATA DATA DATA MSB of Temp —12h
DATA
DATA 0
典范英语官网LSB of Temp
—
RTC/TCXO/Crystal
Address Map
Figure 1 shows the address map for the DS3231 time-keeping registers. During a multibyte access, when the address pointer reaches the end of the register space (12h), it wraps around to location 00h. On an I 2C START or address pointer incrementing to location 00h, the cur-rent time is transferred to a cond t of registers. The time information is read from the condary registers,
while the clock may continue to run. This eliminates the need to reread the registers in ca the main registers update during a read.
I 2C Interface
The I 2C interface is accessible whenever either V CC or V BAT is at a valid level. If a microcontroller connected
decimal (BCD) format. The DS3231 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode lect bit. When high, the 12-hour mode is lected. In the 12-hour mode, bit 5 is the AM/PM bit with logic-high being PM. In the 24-hour mode, bit 5 is the 20-hour bit (20–23 hours). The century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00.
The day-of-week register increments at midnight. Values that correspond to the day of week are ur-defined but must be quential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation.
When reading or writing the time and date registers, c-ondary (ur) buffers are ud to prevent er
lambertrors when the internal registers update. When reading the time and date registers, the ur buffers are synchronized to the internal registers on any START and when the register pointer rolls over to zero. The time information is read from the condary registers, while the clock continues to run. This eliminates the need to reread the registers in ca the main registers update during a read.
The countdown chain is ret whenever the conds register is written. Write transfers occur on the acknowl-edge from the DS3231. Once the countdown chain is ret, to avoid rollover issues the remaining time and date registers must be written within 1 cond. The 1Hz square-wave output, if enabled, transitions high 500ms after the conds data transfer, provided the oscillator is already running.Alarms
The DS3231 contains two time-of-day/date alarms. Alarm 1 can be t by writing to registers 07h to 0Ah. Alarm 2 can be t by writing to registers 0Bh to 0Dh. The alarms can be programmed (by the alarm enable and INTCN bits of the control register) to activate the INT/SQW output on an alarm match condition. Bit 7 of each of the time-of-day/date alarm registers are mask bits (Table 2). When all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers match the corresponding val-ues stored in the time-of-day/date alarm registers. The alarms can also be programmed to repeat every cond, minute, hour, day, or date. Table 2 shows the possi
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ble ttings. Configurations not listed in the table will result in illogical operation.
barry bondsThe DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. If DY/DT is written to logic 0, the alarm will be the result of a match with date of the month. If DY/DT is written to logic 1, the alarm will be the result of a match with day of the week.
When the RTC register values match alarm register t-tings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is t to logic 1. If the corresponding Alarm Interrupt Enable ‘A1IE’ or ‘A2IE’ is also t to logic 1 and the INTCN bit is t to logic 1, the alarm condition will activate the INT/SQW signal. The match is tested on the once-per-cond update of the time and date registers.
Table 2. Alarm Mask Bits
DY/DT
ALARM 1 REGISTER MASK BITS (BIT 7)
ALARM RATE A1M4A1M3A1M2A1M1
X1111Alarm once per cond
X1110Alarm when conds match
X1100Alarm when minutes and conds match
X1000Alarm when hours, minutes, and conds match 00000Alarm when date, hours, minutes, and conds match 10000Alarm when day, hours, minutes, and conds match
DY/DT ALARM 2 REGISTER MASK BITS (BIT 7)
ALARM RATE A2M4A2M3A2M2
X111Alarm once per minute (00 conds of every minute)
X110Alarm when minutes match
X100Alarm when hours and minutes match
冬天的骨头迅雷下载0000Alarm when date, hours, and minutes match
1000Alarm when day, hours, and minutes match
RTC/TCXO/Crystal
ing an acknowledge bit on the last byte that has been clocked out of the slave. In this ca, the slave must leave the data line high to enable the master to gener-ate the STOP condition.
Figures 3 and 4 detail how data transfer is accomplished on the I 2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master
is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most signifi-cant bit (MSB) first.
Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmit-ted by the master. The slave then returns an acknowl-edge bit. Next follows a number of data bytes transmit-ted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the
Figure 2. I
C Data Transfer Overview
Figure 3. Data Write—Slave Receiver Mode
Figure 4. Data Read—Slave Transmitter Mode
RTC/TCXO/Crystal
RTC/TCXO/Crystal
Figure 5. Data Write/Read (Write Pointer, Then Read)—Slave Receive and Transmit
