stm32SystemInit函数详解官⽅固件库中的对应函数为：
void SystemInit (void)
{
/* Ret the RCC clock configuration to the default ret state(for debug purpo) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Ret SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#ifndef STM32F10X_CL
RCC->CFGR &= (uint32_t)0xF8FF0000;
#el
RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F10X_CL */
/* Ret HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Ret HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Ret PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
#ifdef STM32F10X_CL
/* Ret PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEBFFFFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000;
/* Ret CFGR2 register */
RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) /* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
sunris/* Ret CFGR2 register */
RCC->CFGR2 = 0x00000000;
#el
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#endif /* STM32F10X_CL */
#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif
/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
SetSysClock();
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #el
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ #endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be ud by the ur application to tup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwi, any configuration
* bad on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated bad on the predefined
* constant and the lected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz or 25 MHz, depedning on the product ud), ur has to ensure
* that HSE_VALUE is same as the real frequency of the crystal ud.
symantec* Otherwi, this function may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
师范类院校排名* @retval None
*/
⾸先第⼀眼就可以看到函数体中⼏乎全是条件编译。
（1.）先看第⼀⾏代码：RCC->CR |= (uint32_t)0x00000001；显然这是给CR寄存器的最低⼀位赋值为1.官⽅寄存器配置详解截图：
（2.）
#ifndef STM32F10X_CL
RCC->CFGR &= (uint32_t)0xF8FF0000;
#el
RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F10X_CL */
这个条件编译是根据芯⽚容量不同默认初始化CFGR寄存器（Ret SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits ）。官⽅寄存器配置截图（各个位的信息太长，没有截取）：
（3.）
qikRCC->CR &= (uint32_t)0xFEF6FFFF;
RCC->CR &= (uint32_t)0xFFFBFFFF;
显然是把CR寄存器的某些位赋值，其作⽤为：Ret HSEON, CSSON and PLLON ，HSEBYPbits即将HSEON,CSSON,PLLON，HSEBYP位置为零。
（4.）
/* Ret PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
作⽤为把CFGR寄存器的PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE位置0
（5.）
#ifdef STM32F10X_CL
/* Ret PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEBFFFFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000;
/* Ret CFGR2 register */
RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* Ret CFGR2 register */
RCC->CFGR2 = 0x00000000;
#el
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#endif /* STM32F10X_CL */
这个条件编译块的作⽤为根据芯⽚容量初始化中断位（关闭中断位）
glass是什么意思
（6.）
#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif
这个条件编译块的作⽤为初始化Memory控制
(7.)
SetSysClock();
这⾥调⽤了⼀个函数，该函数为：
static void SetSysClock(void)
{dictionaries
北京游戏培训#ifdef SYSCLK_FREQ_HSE
SetSysClockToHSE();
#elif defined SYSCLK_FREQ_24MHz
SetSysClockTo24();
#elif defined SYSCLK_FREQ_36MHz
SetSysClockTo36();
#elif defined SYSCLK_FREQ_48MHz
SetSysClockTo48();
#elif defined SYSCLK_FREQ_56MHz
SetSysClockTo56();
#elif defined SYSCLK_FREQ_72MHz
SetSysClockTo72();
#endif日本童话
/* If none of the define above is enabled, the HSI is ud as System clock
source (default after ret) */
}
我们可以看到该函数就是通过判断定义了哪个宏定义标志符⽽调⽤不同的设置sys时钟频率的函数，官⽅固件库默认定义了SYSCLK_FREQ_72MHz，所以会调⽤SetSysClockTo72这个函数。
如果要使⽤其它频率，那就解开相应注释（只保留⼀个不被注释）。
SetSysClockTo72函数如下：
static void SetSysClockTo72(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
bad romance} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
el
{
HSEStatus = (uint32_t)0x00;
me too 是什么意思
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
