AT89C52 internal structure analysis
Description
口语100The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8Kbytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction t and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash ona monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex rial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operationdown to zero frequency and supports tw
o software lectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, rial port, andinterrupt system to continue functioning. The Power-down mode saves the RAM contentsbut freezes the oscillator, disabling all other chip functions until the next interruptor hardware ret.
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0学习班>tourist是什么意思>博取
Port 0 is an 8-bit open drain bidirectional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be ud as highimpedan
ceinputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during access to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification.External pullups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be ud as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) becau of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, asshown in the following table.Port 1 also receives the low-order address bytes duringFlash programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be ud as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) becau of the internal pullups.Port 2 emits the high-order address byte during fetchesfrom external program memory and during access toexternal data memory that u 16-bit address (MOVX @DPTR). In this application, Port 2 us strong internal pull-ups when emitting 1s. During access to external data memory that u 8-bit address (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.period是什么意思
Port 3
18 and lifePort 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high by th
e internal pullups and can be ud as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) becau of the pullups.Port 3 also rves the functions of various special features of the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.
RST
Ret input. A high on this pin for two machine cycles while the oscillator is running rets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be ud to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature is enabled.
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ALE/PROG
Address Latch Enable (ALE) is an output pul for latching the low byte of the address during access to external memory. This pin is also the program pul input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 th
stone是什么意思e oscillator frequency and may be ud for external timing or clocking purpos. Note, however, that one ALE pul is skipped during each access to external data memory.If desired, ALE operation can be disabled by tting bit 0 of SFR location 8EH. With the bit t, ALE is active only during a MOVX or MOVC instruction. Otherwi, the pin is weakly pulled high. Setting the ALE-disable bit has noeffect if the microcontroller is in external execution mode.
cardioPSEN
Program Store Enable (PSEN) is the read strobe to externalprogram memory.When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
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