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Synchronous FPGA-Bad High-Resolution Implementations of Digital Pul-Width Modulators Denis Navarro,´Oscar Luc´ıa,Member,IEEE,Luis Angel Barrag´a n,Jos´e Ignacio Artigas,Isidro Urriza,
and´Oscar Jim´e nez,Student Member,IEEE
Abstract—Advantages of digital control in power electronics
have led to an increasing u of digital pul-width modulators
(DPWM).However,the clock frequency requirements may exceed
the operational limits when the power converter switching fre-
quency is incread,while using classical DPWM architectures.
In this paper,we prent two synchronous designs to increa the
resolution of the DPWM implemented onfield programmable gate
arrays(FPGA).The propod circuits are bad on the on-chip dig-
ital clock manager block prent in the low-cost Spartan-3FPGA
ries and on the I/O delay element(IODELAYE1)available in the
high-end Virtex-6FPGA ries.The solutions have been imple-
mented,tested,and compared to verify the performance of the
architectures.
Index Terms—Field programmable gate arrays(FPGA),power
conversion,pul-width modulated power converters.
I.I NTRODUCTION
D IGITAL pul-width modulators(DPWMs)have become
a basic building block in digital control architectures
of any power converter[1]–[7].The DPWM frequency is
mainly determined by the power converter operating condi-
tions,whereas the DPWM resolution determines the accuracy
shanghai american schoolin the output voltage/current control.As a conquence,the
DPWM resolution has a direct impact in the power converter
performance.
Traditional DPWM implementations are bad on counters
and comparators,which generate the power converter gating
signals according to veral predefined thresholds[8]–[14].For
the designs,the minimum on-time step is equal to the coun-
terclock period.Its equivalent number of bits n DPW M is
n DPW M=log2
f CLK
f SW
(1)
where f SW is the DPWM frequency and f CLK is the counterclock frequency.Nowadays,power converters are evolving toward de-signs with higher switching frequencies in order to reduce the Manuscript received February8,2011;revid July13,2011and Au-gust29,2011;accepted October20,2011.Date of current version February 27,2012.This rearch was supported in part by the Spanish MICINN un-der Project TEC2010-19207,Project CSD2009-00046,Project IPT-2011-1158-920000,and the FPU grant AP2010-5267,and by the Bosch and Siemens Home Appliances Group.Recommended for publication by Associate Editor L.M. Tolbert.
The authors are with the Department of Electronic Engineering and Communications,University of Zaragoza,Zaragoza50018,Spain(e-mail: denis@unizar.es;olucia@unizar.es;barragan@unizar.es;jiartigas@unizar.es; urriza@unizar.es;ojimenez@unizar.es).
Color versions of one or more of thefigures in this paper are available online at ieeexplore.ieee.
Digital Object Identifier10.1109/TPEL.2011.2173702size of inductors and capacitors.Besides,for the digital imple-mentation,the number of bits n DPW M has to be higher than the A/D converter resolution to avoid limit cycling[15]–[17].As a conquence,an unfeasibly high clock frequency can result, increasing the complexity and the cost of thefinal implementa-tion[18].
Moreover,recent developments in miconductor technol-ogy enable the u of higher switching frequencies through SiC[19]and GaN[20]power devices.This allows the design of power converters with reduced size and cost,and improved dynamic behavior and power density,as shown in[21]and[22]. However,the designs require high-frequency high-resolution PWMs(HRPWMs)in order to take the most of the power converter.
cessna
Anotherfield of application for HRPWMs is the dc–dc con-verters,where either the output voltage[voltage regulator mod-ules(VRMs)],the duty cycle for output-power control[23],or the switching delay mismatch between power devices[24],[25] need to be accurately tuned.As a conclusion,the evolution of both power electronics and digital control techniques makes the development of higher resolution DPWMs[26]necessary.
To overcome this problem,different solutions have been pro-pod depending on whether the digital
controller is imple-mented on a digital signal processor(DSP),an application-specific integrated circuit(ASIC),or afield programmable gate array(FPGA).
In the ca of DSPs,some of them include HRPWM periph-erals[27].The HRPWM module extends the time resolution capabilities of the conventional PWM allowing a minimum time step that is a fraction of the system clock.
Besides,veral architectures have been propod for IC im-plementation[28]–[30].They are usually bad on a tapped delay line in combination with a multiplexer[28]or a hybrid counter/delay line[30].
Several FPGA-bad solutions have also been propod in the literature[31]–[38].One common solution is to u a coar resolution counter-bad stage plus one or veral on-chip digital clock manager(DCM)blocks.The PWM signal is t at the beginning of the counter period,and it is ret after a given number of clock cycles plus a certain fraction of the clock period established by the DCM.
Apart from[35]and[38],the circuits previously published for delaying the ret signal are not fully synchronous.Asyn-chronous circuits make harder to perform static timing analysis and can result in glitching since controlling the logic and routing delays in an FPGA is more difficult than in ASIC imple
shutoff
menta-tions.A synchronous design,therefore,improves the reliability
0885-8993/$26.00©2011IEEE
TABLE I
HRPWM A RCHITECTURE C
考研报名费多少钱
OMPARISON
of the circuit and eas the design process.Besides,it makes the design more independent of the technology,easing the design portability.
In Table I,a brief comparison of the FPGA-bad architec-tures classified according to the coar counter frequency,the achieved resolution,and the number of paths to manually equi-librate is given.The higher the number of paths to equilibrate is,the harder the design of a monotonic DPWM is.Besides,it is pointed out if they are fully synchronous and glitch-free designs,due to the combinational circuit usage.
The aim of this paper is to propo two fully synchronous high-resolution DPWM architectures in order to avoid the need of using unfeasible high clock frequencies,providing a more convenient final implementation.Both of them are bad on the resources available in modern FPGAs.The first propod architecture,prented in [39],is a generalization of the DCM-bad circuit in [35],and it allows operating the circuit at higher clock frequencies [39].The cond proposal is bad on the I/O delay element (IODELAYE1)available in the Virtex-6FP-GAs,and it provides higher resolution with a straightforward implementation.
This paper is organized as follows.The propod high-resolution DPWM architectures using DCM blocks and IODELAYE1blocks are explained in Sections II and III,respec-tively.The experimental results for the propod architectures are shown in Section IV .Section V includes further discussion and some guidelines for the architecture lection.Finally,the conclusions of this study are drawn in Section VI.
II.H IGH -R ESOLUTION DPWM A RCHITECTURE U SING DCM
B LOCKS The key of this architecture is the on-chip DCM block pro-vided in almost every state of the art FPGA (e Fig.1).The following DCM clock management features [40]will be ud.1)Pha s
hifting :The DCM provides four pha-shifted clock signals derived from the source clock CLKIN.In addition to CLK0for zero-pha alignment to the CLKIN signal,the DCM also provides the CLK90,CLK180,and CLK270outputs for 90◦,180◦,and 270◦pha-shifted signals,respectively.Besides,all the outputs of the DCM can be pha shifted with finer resolution.
2)Frequency synthesis:The DCM can generate a wide range of output clock frequencies (CLKFX output port),per-forming clock frequency division and multiplication.Besides pha shifting,the DCM is able to condition the clock input CLKIN in order to obtain clock outputs with 50%
duty
Fig.1Simplified pinout description of the DCM
block.
Fig.2.Fixed fine pha shifting effect.
cycle.The clock feedback signal CLKFB is ud to compare and lock the output signals with the input CLKIN signal.
The fine pha shifting can be fixed (specified at design time and t during the FPGA configuration process)or variable.It is t by means of the DCM attribute PHASE_SHIFT,an integer in the range [−255,+255].Fig.2shows the fine pha shift effects in the fixed mode of operation.A pha-shifted output with a resolution of (1/256)th of the input clock period can be obtained.
The variable pha-shifting feature has been ud in [33].However,this operating mode requires veral clock cycles to change the duty cycle,degrading the dynamic performance.Besides,an asynchronous circuit is ud to divide the clock cycle into four quadrants.In this paper,a fully synchronous design with fixed pha shifting is propod.A.First Approach
In order to introduce the propod DCM-bad high-resolution DPWM architecture,let us consider a first version to obtain a 2-bit resolution increa (e Fig.3).This architec-ture is basically the one prented in [35].
NA V ARRO et al.:SYNCHRONOUS FPGA-BASED HIGH-RESOLUTION IMPLEMENTATIONS OF DIGITAL PULSE-WIDTH MODULATORS
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Fig.3.DCM-bad HRPWMfirst approach.birthdate
In thisfirst version,the quadrant pha-shifted outputs of a single DCM are ud.The duty cycle command dc(m:0)has m+1bits,ranging from m to0,and the counter“CNT”has m−1bits.“CLRD”signal is t when the m−1most-significant bits(MSBs),dc(m:2),are equal to CNT;and SETD signal is t when CNT is equal to zero and dc(m:2)is different from zero. Fig.4shows how the circuit works with m=4,and dc =“10010”.Basically,when the counter CNT is equal to the m−1MSBs of the duty command dc,signal CLRD activates. The resulting pul is captured in the next clock cycle by FF0, and pha shifted90◦,180◦,and270◦byflip-flops FF1,FF2, and FF3,respectively.The four FFs implement a multipha synchronous circuit[41].The two least-significant bits(LSBs) of the duty command are ud by the multiplexer to lect the pha-shifted signal that clears the SR latch.
The advantage of this proposal in relation to others is that the digital circuit that generates the ret of the SR latch is synchronous.The u of asynchronous circuits to ret the latch makes harder to calculate timing using static timing analysis and can result in glitching since controlling the logic and routing de-lays in an FPGA is more difficult than in ASIC implementations. The next ction prents
festival walkan improved and scalable architecture in order to improve the HRPWM resolution.B.Generalization of the DCM-Bad Architecture
The previous architecture can be scaled to enhance the
HRPWM resolution.Let n=m+k be the bits of the duty
cycle command dc,with k≥2.Basically,the propod circuit
is made up of a synchronous m-bit counter,r DCMs,p=4×r
edge-triggeredflip-flops,a p-to-1multiplexer,and an SR latch
who output is the PWM signal.The modulus of the counter is
批准英文
configurable.
The CLRD signal is t when the counter is equal to the
m MSBs of dc.The SETD signal is t when the counter is zero and dc is different from zero.The signals are ud
to generate the SET and RESET signals that control the SR
latch.
The counter and all DCMs are clocked by the same input clock
signal“CK.”Quadrant pha-shifted outputs CLK0,CLK90,
CLK180,and CLK270of DCMs are ud to generate a t of p
pha-shifted clocks{CK i}with0≤i<p.All clock signals CK i have the same period T CK with50%duty cycle.CK i is
pha-shifted T CK/p time with respect to CK i−1[e Fig.5(a)].
Thefine pha shifting in thefixed mode shifts the pha of
all DCM output signals by afixed fraction of the input clock
period.Being the minimum pha shift1/256of T CK(k≤8),
2518IEEE TRANSACTIONS ON POWER ELECTRONICS,VOL.27,NO.5,MAY
2012
Fig.4.DCM-bad HRPWM operation with dc =
“10010.”
Fig.5.
(a)Phad clock signals.(b)Multipha synchronous circuit.
the pha-shift value for DCM j must be t to j ×64/r with 0≤j <r .
The p flip-flops [e Fig.5(b)]implement a multipha syn-chronous circuit.FF i is triggered by the rising edge of CK i .A p -to-1multiplexer us the k LSBs of dc to lect the CLR i signal that clears the SR latch.CLR i is delayed by a fraction 1/p of T CK with respect to CLR i −1.In order to improve speed,
the circuit is designed,such as the minimum allowable delay for paths,in which the source and destination clocks are different,is T CK /2,regardless the pha number.By doing so,the max-imum clock frequency is not limited by the multipha circuit but for the DCM,and it can be easily scaled to the required p number.In the circuit shown in Fig.5(b),the period constraint is less restrictive than in the previous design,and a higher clock frequency can be achieved:
t p max (FF i )+t p max (net)+t SU FF p/2+i
<
T CK i
2−δmax CK i ,CK p/2+i
(2)where t p max (FF i )and t SU FF p /2+i
are the maximum clock-to-output propagation time and the tup time of a flip-flop,respectively;t p max (net)is the routing delay,T CK0/2is the nom-inal time difference between rising edges of CK0and CK2,and δmax (CK0,CK2)is the maximum difference in the arrival time of the rising edges of CK0and CK2in relation to its nominal value.
For a particular FPGA ries,the value of p is constrained by the number of DCM blocks available,the number of global clock lines that each DCM block can drive up,and the need to ensure that the routing delay of the multiplexer inputs is less than T CK /p for a monotonic behavior.
C.Implementation
This ction describes an implementation example carried out to show the feasibility of the DCM-bad HRPWM architecture propod in this study.As the implementation depends on the FPGA,let assume that the high-resolution DPWM is imple-mented in the Xilinx XC3S500E Spartan-3E FPGA o
f the S-3E Starter Kit board by Digilent.This board includes a 50-MHz clock oscillator that is ud as the input clock.
As the FPGA has four DCMs,the parameter k can be up to 4.As an example,Fig.6shows an implementation with m =8,
NA V ARRO et al.:SYNCHRONOUS FPGA-BASED HIGH-RESOLUTION IMPLEMENTATIONS OF DIGITAL PULSE-WIDTH MODULATORS
河南2011高考分数线
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Fig.6.Implemented high-resolution DPWM with m=8and k=3.
胡歌英文演讲视频and k=3.It has been described in VHDL.DCMx4multiplies its input clock frequency by4.The CLKFX output of DCMx4is connected to the input clock of the counter,DCM0and DCM1. The binary counter has8bits,and SETD and CLRD signals are generated from the counter output and the eight MSBs of dc as explained earlier.FFa and FFb store the signals.Negative-edge-triggeredflip-flops FFc and FFd avoid malfunctions due to the pha offt between CK and CK0(±200ps max.according to the data sheet).
DCM0and DCM1generate eight phad clocks{CK0,..., CK7}.PHASE-SHIFT attribute of DCM0is t to0.DCM0 generates clocks CK0,CK2,CK4,and CK6.PHASE-SHIFT at-tribute of DCM1is t to32,and its outputs are shifted32/256 of T CK.DCM1generates clocks CK1,CK3,CK5,and CK7.In the implementation step of the designflow,DCM0and DCM1 are manually placed at DCM_X0Y0and DCM_X1Y0,respec-tively,in order to be clo to each other and reduce routing de-lays.The two DCMs can drive up to four global clock lines. Then,the circuit must work with the rising and falling edges of only four phad clocks{CK0,CK1,CK2,CK3},and FF4,FF5, FF6,and FF7must be negative-
edge triggered.This introduces nonlinearity in the on-time step due to duty-cycle variation but this effect cannot be solved due to the routing architecture of this FPGA.
For this implementation,the maximum clock frequency is limited to200MHz,which is the maximum operating frequency for the CLK90and CLK270DCM outputs according to the FPGA datasheet.However,it is important to note that if there were paths in the implementation in which the difference be-tween active clock edges of source and destinationflip-flops were lower than the one prent in this design(T CK/2),the tim-ing constraint would be more restrictive than the one expresd in(2)and the maximum clock frequency would be reduced.For instance,a clock difference of T CK/4,as it occurs in Fig.3, would lead to the168-MHz maximum operating frequency.In this ca,the multipha circuit would limit the operation in-stead of making the most of the FPGA DCM resources.
The propod architecture can also be implemented using the high-end Virtex-6FPGA ries.In the FPGAs,the DCM block has been replaced by the mixed-mode clock manager (MMCM),which provides improved functionalities and jitter performance.The MMCM provides output signals with a45◦pha shift.The DCM0and DCM1can therefore be replaced by a single MMCM,and a higher resolution can be achieved
