Error correction architecture to increa speed an

更新时间:2023-06-13 03:05:38 阅读: 评论:0

专利名称:Error correction architecture to increa
speed and relax current drive requirements
lesion
of SAR ADC
affected
发明人:Chakravarthy Srinivasan,Kiran M. Godbole
申请号:US10152423
美国英语语言学院申请日:20020521
the tower
手表的英语公开号:US20030123646A1obrvation
公开日:
20030703
专利内容由知识产权出版社提供nsation什么意思
ekaterina makarova专利附图:
must
摘要:An SAR ADC is operated by sampling an input voltage and redistributing a
corresponding charge among the coupling capacitor and a plurality of binarily weighted
capacitors of a CDAC array to produce a first voltage on a charge summing conductor. A successive approximation bit testing/conversion operation is performed at a first speed on a first group of bits, beginning with the MSB, to determine the bits of the first group with at least a first level of accuracy. A first error correction operation includes performing a bit testing/conversion operation on a last bit of the first group at a cond speed which is lower than the first speed to determine the bits of the first group at least a cond level of accuracy which is more accurate than the first level of accuracy. Both the voltage on the charge summing conductor and the bits of the group are incremented or decremented as necessary to elevate the level of accuracy of bits of the first group to at least the cond level of accuracy.
agp是什么意思
申请人:TEXAS INSTRUMENTS INCORPORATED
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