Fast High Voltage Switching With SiC Majority Carrier Devices
Tsuyoshi FUNAKI
Osaka University, Division of Electrical, Electronic and Information Engineering, Graduate School of Engineering, 2-1 Yamada-Oka, Suita, Osaka, 565-0871, Japan
翻译公司介绍
Raising operation voltage of power conversion circuit is effective in reducing conduction loss. It requires power switching device to have high breakd own voltage. High voltage Si power d evice requires bipolar operation to red uce cond uction loss sufficiently. However, bipolar operation worns the switching characteristics of the d evice especially in turn off operation; such as rever recovery for PiN diode and tail current for IGBT. The high critical electric field of SiC micond uctor realizes high break d own voltage majority carrier device with substantially low on resistance. It can achieve fast switching capability for it only requires cond ucting and blocking majority carrier in the d evice for switching operation. This paper demonstrates the fast high voltage switching operation of SiC Schottky barrier d iod e (SBD) and MOSFET with comparing to the conventional Si device.
Introduction
Power electronics converts and control electric power with the u of switching operation of power miconductor device and small capacity energy storage component for dealing switching energy. The power conversion technology is indispensable for energy saving, functionalizing and value adding in the usage of electricity. Higher breakdown voltage, lower conduction loss and faster switching capability of the power miconductor device is required to attain further efficiency and performance of power conversion circuit. Si power d evice has been d eveloping and improving in the d evice structure and manufacturing process, and Si IGBT [1] and super junction (SJ) MOSFET [2] were invented and put into practical u. However, the performance of the d evices approaches the theoretical limitation resulting from micond uctor property of Si. Therefore, wid e band gap micond uctor material has been attracting attention to overwhelm Si micond uctor limit, and SiC takes a lead in the d evelopment of power switching device [3, 4, 5]. The critical electric field of SiC miconductor is greater by a d egree of magnitud e than Si micond uctor. This makes SiC power switching d evice possible to employ unipolar d evice structure for high break d own voltage ratings with high impurity concentration in voltage blocking d rift region, where conventional Si power switching d evice is required to employ bipolar d evice structure for lowering conduction resistance. This paper focus on SiC MOSFET and Schottky barrier diode (SBD) as a power switching d evice, and d emonstrates and evaluates their switching characteristics with comparing to the switching characteristics of conventional Si IGBT and Si SJ MOSFET.
10.1149/05003.0085ecst ©The Electrochemical Society
ECS Transactions, 50 (3) 85-92 (2012)
Experimental tup and switching of SiC SBD
Double pul test circuit
The switching characteristics of SiC MOSFET for resistive load are stud ied in the previous work [6]. This paper studies the switching characteristics of SiC MOSFET for ind uctive load with freewheeling d iod e clamp. The circuit d iagram ud for the experiment is shown in Fig. 1(a). The drain voltage of MOSFET in turn off process is clamped with power supply voltage, and the ind uctor current is hold by commutating MOSFET drain current to the freewheeling diode, where SiC SBD is installed. Thus, this circuit configuration d oes not ind uce over voltage originated from d i/d t of ind uctor current and also the switching characteristics of the freewheeling diode can be evaluated at the same time in this circuit configuration.
The quence of experimental circuit operation for switching characterization called d ouble pul method is illustrated in Fig. 1(b). No current is flowing in the MOSFET, d iod e, and ind uctor for the
initial cond ition. The MOSFET begins cond ucting and flowing d rain current through ind uctor with applying 1st firing pul to the gate of MOSFET. The drain current increasing rate is determined with the power supply voltage E and ind uctance L by d i/d t = E/L, and the gate pul is hold applying until the d rain current is incread to the desired value. The MOSFET turns off when the applied gate pul is removed. Then, the drain current flowing through MOSFET commutate to the anod e current of freewheeling d iod e. The ind uctor current barely d ecreas and the magnitude of the diode current is kept almost constant during freewheeling period, for the induced voltage across the inductor is low, which corresponds to the voltage drop at the diode and wiring resistance. Therefore, the almost intact power supply voltage is applied on the MOSFET in blocking condition. The MOSFET turns on again when the cond gate pul is applied to the MOSFET. The current flowing through the freewheeling d iod e commutates to the MOSFET for the d iod e turns off by imposing power supply voltage as the rever bias voltage. The rever recovery phenomenon of the d iod e is obrved for this turn off operation.
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Figure 1. Switching test tup for double pul characterization method.
Switching characteristics of SiC SBD
The rever recovery phenomenon in turn off operation of freewheeling diode in the experimental circuit is studied for SiC SBD. An SBD is operated with a majority carrier
in the micond uctor and only majority carrier is swept out and d epleted in turn off operation. Figure 2(a) shows the anode current respon in turn off operation of diode to the d ifferent parameter of forward cond uction current of d iod e. The peak rever recovery current barely changes with the forward conduction current for the same rever bias voltage. That is, no minority carrier injection effect is obrved.
Figure 2(b) shows the anod e current respon in turn off operation of d iod e to the d ifferent current d ecaying rate d i/d t in current falling ed ge. The parameter of turn off current d ecaying rate is regulated with the gate resistance Rg of the MOSFET. The injected minority carrier in the d rift region of the d iod e recombines d uring turn off process and longer turn off transition time with small d i/d t increas the amount of recombined charge in bipolar operation. The results do not show the dependency on di/dt of turn off current decaying rate in the rever recovery current. Therefore, the results clarify the majority carrier device characteristics of the SiC SBD and the fast switching capability of SiC SBD.
(a)Forward current dependency. (b) dt/dt dependency.
Figure 2. Turn off characteristics of SiC SBD.
Switching characteristics of SiC MOSFET
The switching characteristic of SiC MOSFET for the d iod e clamped ind uctive load is stud ied in this ction. The results for Si IGBT and Si SJ MOSFET are shown for comparative study.
Static characteristics
The static characteristics of the studied devices are evaluated here as the reference in evaluating switching characteristics. The d rain current and d rain (gate) voltage (I-V) characteristics are stud ied to evaluate the cond uction loss and operation point in switching operation. The terminal capacitance and bias voltage (C-V) characteristics are evaluated to estimate switching dynamics.
I-V characteristics. The static I-V characteristics of studied devices are shown in Fig.
3. Fig. 3(a) shows the forward conduction I-V characteristics for gate voltage Vgs=20V. The SiC MOSFET gives the lowest on resistance of 0.2ohm in linear region. Though, Si SJ MOSFET has larger die size than the other devices, but gives 0.9ohm on resistance,
which is 4.5 times higher than SiC MOSFET. Si IGBT gives knee voltage of 1V stemming from PN junction, but gives lowest d ifferential resistance by cond uctivity modulation. The forward voltage drop of Si IGBT corresponds with SiC MOSFET and Si SJ MOSFET at 13A and 1A, respectively.
Fig. 3(b) shows the forward transfer characteristics. SiC MOSFET and Si SJ MOSFET gives threshold gate voltage around 4V, and Si IGBT gives higher 7V threshold gate voltage. This d ifference in threshold gate voltage affect on the turn on delay time. The transfer conductance of the devices are 2.22S, 4.32S and 5.64S for SiC MOSFET, Si SJ MOSFET and Si IGBT, respectively, which are extracted from d rain current for 2A< Id s <8A. This d ifference is small and may result in no significant difference in Miller effect in switching operation.
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s-Vgs characteristics. Figure 3. I-V characteristics of the studied device.
C-V characteristics. The terminal capacitance of the d evice must be charged or discharged during s
witching operation, which results in the dynamic behavior. The drain and gate voltage dependency in the terminal capacitance of the device is shown in Fig. 4. Fig. 4(a) shows the gate voltage dependency of input capacitance (Ciss=Cgs+Cgd) for the stud ied d evices with Vd s=0V cond ition. The d epletion, inversion, and accumulation of carrier underneath the gate electrode in the device depending on the applied gate voltage is obrved as the change in capacitance. Si IGBT has almost twofold input capacitance to the other devices. Though, there is a difference in the capacitance variation to the gate voltage, but SiC MOSFET and Si SJ MOSFET has more or less the same input capacitance. The difference in input capacitance is not significant, then the rate of gate voltage change by gate d riving in blocking cond ition of the d evice are expected to be similar for same gate resistance.
Fig. 4(b) shows the drain voltage dependency of feedback capacitance (Crss=Cgd) for the experimented devices with Vgs=0V. Si SJ MOSFET gives larger Crss than the other type devices in low drain voltage region, but it becomes smaller than SiC MOSFET for Vds>20V and Si IGBT for Vds > 50V. The large variation of Crss in Si SJ MOSFET to the applied d rain voltage stems from d epletion of large area in the super junction structure, and results in the difference of Miller effect with the drain voltage.
Fig. 4(c) shows the drain voltage dependency of the output capacitance (Coss) for the experimented d evices in blocking cond ition with Vgs=0V. The output capacitance consists of drain-source capacitance Cds and feedback (drain-gate) capacitance Cgd. The output capacitance of Si SJ MOSFET largely changes for drain voltage around 30V to 50V, where the feedback capacitance largely changes as shown above. This also results
英语听力材料from the d epletion in the SJ region with the applied d rain voltage. On the other hand , output capacitance of SiC MOSFET and Si IGBT changes log-linearly with the applied drain voltage, which is resulting from the expansion of depletion in the uniformly doped plane drift region.
The input capacitance, feed back capacitance, and output capacitance respectively affect on the ramp up of gate voltage, Miller effect, and the buildup of drain voltage in switching operation. The next ction evaluates the influence of the difference in terminal capacitance on the switching behavior of the devices.
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(a) Ciss-Vgs characteristics. (b) Crss-Vds characteristics. (c) Coss-Vds characteristics. (V d s=0V) (Vgs=0V) (Vgs=0V) Figure 4. C-V characteristics of the studied device.
Switching characteristics
The turn on and turn off switching operation of SiC MOSFET is stud ied and compared with other type of devices in this subction.
Turn on operation. The switching characteristics in turn on operation is demonstrated and evaluated
here with the parameter of applied d rain voltage in blocking cond ition, which gives the difference in the amount of depleted charge for output capacitance. The cond uction current in the final cond ition barely affects on the behaviors in the state transition period. Then, one ca of drain current Ids=10A is prented in the following discussion of turn on operation.
Figure 4 (a), (b) and (c) show the measured gate voltage Vgs, drain current Ids, and drain voltage Vds, for SiC MOSFET, Si SJ MOSFET and Si IGBT, respectively. Each d evice begins to flow d rain current at the instant when the gate voltage ri up to the respective threshold gate voltage. The d rain current build s up with high rate d i/d t in accord ance with the ramp up of gate voltage. The d rain voltage is clamped with the power supply voltage during the period of current commutation from freewheeling diode to the MOSFET, for the anode voltage of freewheeling diode does not ri up during its turn off process due to conrved inductor current. However, the induced voltage which is given by the product of parasitic circuit inductance L in the drain current path and high rate di/dt, is superimpod on the power supply voltage. Then, it is obrved as the dip in drain voltage in this period. All the experimented result is measured with the same circuit. Thus the parasitic ind uctance is same in each ca. The magnitud e of the voltage d ip almost coincides in all results; therefore all the device give same maximum current ramp up rate di/dt. The voltage recovery from the dip is ob
rved for Si SJ MOSFET and Si IGBT, but the recovery is not obrved for SiC MOSFET. This ind icates that the SiC MOSFET keeps high di/dt to the final state of current ramp up. The drain voltage starts to fall soon after the drain current is established. The high rate of voltage fall is obtained for
SiC MOSFET and Si SJ MOSFET. But, it takes longer time to completely fall down the drain voltage of IGBT, due to forward recovery in sufficiently modulating conductivity by minority carrier injection. The high rate d v/d t in d rain voltage falling ed ge also induces voltage dip in gate voltage Vgs with capacitive coupling of Cgs and Cgd. The voltage dip in Vgs for Si IGBT is smallest for it has largest input capacitance.pledge
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高一数学教材Figure 5. Turn on respon.
Turn off operation. The switching characteristics in turn off operation is demonstrated and evaluated here with the parameter of forward drain current in conducting condition. The different blocking drain voltage in the final condition has less effect on the behavior in the state transition period. Then, only Vd s=300V ca is prented in the following discussion of turn off operation.
The drain current starts to decrea when the conduction resistance begins to increa with the reducing gate voltage. That is, the operation point in I-V plane shifts from linear region to saturation region. The turn off d elay time in beginning to fall d rain current becomes shorter in larger conduction current condition. Becau, the operation point for larger conduction current is clor to the saturation region. Therefore, Si SJ MOSFET has shortest delay time for it has smallest saturation current.
The d i/d t of d rain current in turn off operation ind uces voltage with the parasitic inductance in drain current path. This results in over voltage with superimposing on drain voltage, which becomes more vere in higher di/dt of current falling edge. The parasitic inductance in the experimental circuit is th
e same to the each device, and almost the same peak voltage indicates more of the same of the peak drain current falling rate di/dt. The d rain voltage begins to build up before completely blocking d rain current, and the completion of voltage build up becomes faster in larger cond uction current d ue to less
