Power Management11 This ction focus on the 82443BX power management features only. The PIIX4E datasheet
along with this ction provide the complete system power management description.
11.1Overview
11.1.1Power Management Features Supported by the 82443BX
•Suspend Resume
•Clock Control
•SDRAM Power Down Mode
•SMRAM
•ACPI and PCI-PM
11.1.2Low-Power Modes Supported by the 82443BX
The 82443BX supports a variety of system-wide low power modes using the following functions:
•Hardware interface with PIIX4E is ud to indicate:
—Suspend mode entry.
—Resume from suspend.
—Whether to ret “resume logic” during resume from Suspend to Disk (STD).
—Whether to automatically switch from suspend to normal refresh
•Automatic transition from normal to suspend refresh.
•Optional automatic transition from suspend to normal refresh.
•Optional CPU ret during resume from Power On Suspend (POS).
•Variety of Suspend refresh types:请说话
—Self Refresh for SDRAMs.
—Optional Self Refresh for EDO.
—Optional CAS Before RAS (CBR) refresh for EDO. Integrated Ring oscillator is ud to provide the time ba for the associated logic.
—Programmable slow refresh, relevant for CBR refresh only.
•I/O pins isolation to significantly reduce power consumption while in POS and STR modes.
Bad on the above functions, the 82443BX distinguishes the following system-wide low power
modes:
•STR and POS suspend entry and exit are generally handled in the same manner. The following exceptions are related to POS:
—POS resume quence may or may not include CPU ret. STR, with PCIRST# active always includes CPU ret.
—POS resume quence requires hardware transition from suspend to normal refresh. STR, with PCIRST# active requires software initiated transition.
•STD resume is handled the same as power on quence, including complete ret of 82443BX state.
11.1.3Clock Control Functions Supported by 82443BXyoubastard
•Internal clock gating: this function allows the 82443BX to gate the clock to the majority of its logic while there is no pending events to handle.
•The Primary PCI bus includes the support of the CLKRUN#, which enables the PIIX4E to dynamically disable the primary PCICLK and for the 82443BX and PCI peripheral to re-
enable the clock when it is needed to perform a transaction.
•When an AGP port is not available on the system, a strapping option allows the 82443BX to permanently disable all clocks associated with AGP logic.
11.1.4SDRAM Power Down Mode
The 82443BX supports SDRAM power down mode. The 82443BX also provides a capability to
dynamically enter the SDRAM into low power mode when DRAM rows are idle and resume
DRAM activity when transactions request the access to DRAM.
11.1.5SMRAM Functions
The 82443BX provides the normal SMRAM range mapping, in the areas below 1MB, as well as
extended SMRAM ranges that are mapped in cacheable ranges above 1MB. In addition, the
82443BX provides the normal control mechanism to initialize, clo for data access and lock the牛津英语教研网
SMRAM range.
Summary of ACPI Functions英语日记50字
The 82443BX provides an optional decoding of pm2_control register in IO port 22h. This IO port
can be ud to disable the 82443BX arbiters for PCI and AGP initiated cycles.
Desktop vs. Mobile Power Management Functions
In general, all mobile functions of the 82443BX are available in the desktop configuration. Due to
system design limitations, however, certain functions are not supported in a desktop environment
(i.e., POS/C3 state).
In Mobile systems, when system exits low power modes such as deep sleep or POS, the AGP
devices should not generate a request, using AGP mantics, for a duration of at least 33 uc.
System Power Modes
Table11-1 provides an overview of how the above features map into system-wide low power
modes.
11.282443BX Ret
The 82443BX ret function is an integral part of the suspend resume functions. The 82443BX supports the normal ret function in a desktop platform, as well as the various power-up ret and resume ret functions in the mobile platform. In this ction, the power-up ret is described. The resume from suspend quences are described in the following ction.
Table 11-1. Low Power Mode System Suspend State 82443BX
State Description POS Exit
PCIRST External Clk HCLK PCLK
HCLK
PCLK Powered-On ON The 82443BX is fully on and
operating normally.
Internal clock gating as well as PCI
CLKRUN# may be enabled.
N/A Active Active CPU STOP_GRANT / QUICK_START (C2)ON This is transparent to the 82443BX
as external HCLK and PCLK are
doodunaffected. Host Bus is Idle however.
Internal clock gating as well as PCI
CLKRUN# may be enabled.
N/A Active Active CPU STOP CLOCK (C3)(DEEP SLEEP)POS HCLK clock is kept low. The 82443BX maintains DRAM refresh
using suspend refresh.
N Low Low or Active Powered On Suspend (POS, POSCL)POS The only running clock is the RTC
clock. The 82443BX maintains
DRAM refresh using suspend
乱七八糟英文
refresh. When resume, the 82443BX
may or may not generate CPU ret.
N Low Low Powered On Suspend (POSCL)The only running clock is the RTC
clock. The 82443BX maintains
DRAM refresh using suspend
refresh. On resume, PIIX4E
generates PCI ret.
Y Low Low Suspend to RAM (STR)POS CPU and other components (with the
exception of DRAM and PIIX4E
resume logic) are assumed to be
powered OFF.
The 82443BX maintains DRAM
refresh using suspend refresh. All
82443BX logic, with the exception of
resume and refresh are inactive.
Y Low Low Suspend -to-Disk (STD) or Powered-Off OFF Entire system is powered OFF
except for PIIX4E resume and RTC
wells. Upon resume, the 82443BX
rets its entire state.N/A X X
11.2.1CPU Ret
The CPU ret is generated by the 82443BX in the following ca:
•CPURST# is always asrted if PCIRST# is asrted.
•CPURST# is asrted during resume quence from POS CRst_En= 1.
Table 11-2. AGPt Ret
Table 11-3. Ret Signals Signal Asrted with
PCIRST#
System Devices or Bus Affected Signal Source Description PCIRST#-PCI bus, 82443BX
哺乳动物的意思NB, PIIX4Egenius
PIIX4E PCIRST# is ud in power -up quence as well as resume from STR or STD. CPURST#Always CPU
82443BX CPU ret signal. CPURST# pin resides in 82443BX.RSTDRV Always ISA bus / X-Bus
惊喜的英文怎么读devices PIIX4E ISA bus ret. Directly derived from PCIRST#. Resides in PIIX4E main
voltage well.
SUS_STAT#N/A PIIX4E only SUS_STAT# signals a suspend mode
entry and exit. Both signals originate
from PIIX4E in its suspend voltage well.
INIT#No CPU PIIX4E CPU Soft Ret generated by PIIX4E.External CPU
Clock Ratio
Straps External CPU Strap Glue A20M#, IGNNE#,
INTR, NMI RSTDRV
SUB_STAT1#
PCIRST#
PIIX4E#
NBX#P WROK
I NIT#
CRESET#CPURST#
Pentium ® Pro
Processor
4x
2to1 Mux
The 82443BX deasrts CPURST# 1 ms after detecting the rising edge of PCIRST#. The CPURST# is synchronous to host bus clock.
PCIRST# must be asrted when the system resumes from low power mode of which power is removed, including resume from STR or STD and power up quence. In the cas, CPURST# is activated with the assumption that CPU power is removed as well and in order to enforce correct resume quence.
When resuming from POS, the PCIRST# and CPURST# are typically not ud, to speed up the resume quence. The option to ret the CPU, in this ca, is available by using the CRst_En configuration bit option.
When the ur performs a soft ret, the PIIX4E drives SUSTAT# to the 82443BX. This forces the 82443BX to switch to a suspend refresh state. When the BIOS attempts to execute cycles to
DRAM, the 82443BX will not accept the cycles becau it believes that it is in a suspend state. After coming out of ret, software must t the Normal refresh enable bit (bit4, Powerexistent
Management Control register at Offt 7Ah) in the 82443BX before doing an access to memory.
11.2.2CPU Clock Ratio Straps
The Pentium Pro processors require their internal clock ratio to be t up via strapping pins multiplex
ed onto signals A20M#, IGNE#, INTR, and NMI. The signals should reflect the
strapping values during the deasrted edge of CPURST# signal and be held stable for between 2 to 20 clocks. HCLKs after CPURST# is deasrted.
The 82443BX is designed to support CPU strapping options with external logic, when PIIX4E is ud. Figure 11-2 illustrates the strapping pin timing when using the external glue logic (necessary for PIIX4E). The external mux is switched via the CRESET# signal which is a 2 clock delayed version of CPURST#.
Figure 11-1. Ret CPURST# in a Desktop or Mobile System When PCIRST# Asrted
