UCC1946UCC2946UCC3946
SLUS247B - FEBRUARY 2000
registry
FEATURES
•Fully Programmable Ret Threshold •Fully Programmable Ret Period •Fully Programmable Watchdog Period •2% Accurate Ret Threshold •VDD Can Go as Low as 2V •18µA Maximum IDD •
Ret Valid Down to 1V
Microprocessor Supervisor with Watchdog Timer
BLOCK DIAGRAM
DESCRIPTION
The UCC3946is designed to provide accurate microprocessor supervi-sion,including ret and watchdog functions.During power up,the IC asrts a ret signal RES with VDD as low as 1V .The ret signal re-mains asrted until the VDD voltage ris and remains above the re-t threshold for the ret period.Both ret threshold and ret period are programmable by the ur.The IC is also resistant to glitches on the VDD line.Once RES has been deasrted,any drops below the threshold voltage need to be of certain time duration and voltage mag-nitude to generate a ret signal.The values are shown in Figure 1.An I/O line of the microprocessor may be tied to the watchdog input (WDI)for watchdog functions.If the I/O line is not toggled within a t watchdog period,programmable by the ur,WDO will be asrted.The watchdog function will be disabled during ret conditions.The UCC3946is available in 8-pin SOIC(D),8-pin DIP (N or J)and 8-pin TSSOP(PW) packages to optimize board space.
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ELECTRICAL CHARACTERISTICS:Unless otherwi specified,VDD = 2.1V to 5.5V for UCC1946 and UCC2946;
VDD = 2V to 5.5V for UCC3946; TA = 0°C to 70°C for UCC3946, –40°C to 95°C for UCC2946, and –55°C to 125°C for UCC1946;T A =T J
PARAMETERS
TEST CONDITIONS
MIN TYP MAX
MIN TYP
MAX UNITS UCC3946
UCC1946 & UCC2946
Operating Voltage 2.0
5.5 2.1
5.5V Supply Current 10181218µA Minimum VDD (Note 1)
1 1.1
V
Ret Section Ret Threshold VDD Rising
1.210
1.235 1.260
1.170
1.235 1.260
V Threshold Hysteresis 15
15
mV Input Leakage 5
5
nA Output High Voltage I SOURCE = 2mA V DD –0.3
V DD –0.3
V Output Low Voltage I SINK = 2mA
te
0.10.1V VDD = 1V,I SINK = 20uA 0.2
0.4
V VDD to Output Delay VDD = -1mV/µs (Note 2)120120µs Ret Period C RP = 64nF
160
200
260
140
开心学日语200
320
ms
Watchdog Section WDI Input High 0.7·V DD
0.7·V DD
V WDI Input Low 0.3·V DD 0.3·V DD V Watchdog Period C WP = 64nF
1.12 1.60
2.08
0.96 1.60
2.56
s Watchdog Pul Width 5050ns Output High Voltage I SOURCE = 2mA V DD –0.3
V DD –0.3
V Output Low Voltage
I SINK = 2mA 0.1
0.1
V
Note 1:This is the minimum supply voltage where RES is considered valid.Note 2:Guaranteed by design.Not 100% tested in production.
ABSOLUTE MAXIMUM RATINGS
三月英文简写
V IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C Junction Temperature. . . . . . . . . . . . . . . . . . .–55°C to +150°C Lead Temperature (Soldering, 10 c.). . . . . . . . . . . . .+300°C Currents are positive into,negative out of the specified terminal.Consult Packaging Section of the Databook for thermal limita-tions and considerations of packages.
The UCC3946supervisory circuit provides accurate re-t and watchdog functions for a variety of microproces-sor applications.The ret circuit prevents the microprocessor from executing code during undervoltage conditions,typically during power-up and power-down.In order to prevent erratic operation in the prence of noi,voltage “glitches”who voltage amplitude and time duration are less than the values specified in Fig.1are ignored.8890
The watchdog circuit monitors the microprocessor’s ac-tivity,if the microprocessor does not toggle WDI during the programmable watchdog period WDO will go low,alerting the microprocessor’s interrupt of a fault.The WDO pin is typically connected to the non-maskable in-put of the microprocessor so that an error recovery rou-tine can be executed.
APPLICATION INFORMATION
Figure 1.Overdrive voltage vs.delay to output low on RESB.
Slew rate:–1V/mS;monitored voltage =V DD .
GND:Ground reference for the IC.
RES:This pin is high only if the voltage on the RTH has rin above 1.235V .Once RTH ris above the threshold,this pin remains low for the ret period.This pin will also go low and remain low if the RTH voltage dips below 1.235V for an amount of time determined by Figure 1.RTH:This input compa
res its voltage to an internal 1.25V reference.By using external resistors,a ur can pro-gram any ret threshold he wishes to achieve.
RP:This pin allows the ur to program the ret period by adjusting an external capacitor.
VDD:Supply voltage for the IC.
WDI:This pin is the input to the watchdog timer.If this pin is not toggled or strobed within the watchdog period,WDO is asrted.
WDO:This pin is the watchdog output.This pin will be asrted low if the WDI pin is not strobed or toggled within the watchdog period.
WP:This pin allows the ur to
program the watchdog period by adjusting an external capacitor.
PIN DESCRIPTIONS
Figure 2.Typical RTH perature.
Figure 3.Typical IDD vs VDD.
Programming the Ret Voltage and Ret Period The UCC3946allows the ret trip voltage to be pro-grammed with two external resistors.In most applications VDD is monitored by the ret circuit,h
owever,the de-sign allows voltages other than VDD to be monitored.Referring to Fig.4,the voltage below which ret will be asrted is determined by:
V =1.235•
R1+R2R2
RESET In order to keep quiescent currents low,resistor values in the megaohm range can be ud for R1and R2.A man-ual ret can be easily implemented by connecting a mo-mentary push switch in parallel with R2.RES is guaranteed to be low with VDD voltages as low as 1V .Once VDD ris above the programmed threshold,RES remains low for the ret period defined by:
T C RP RP
=•3125.where T RP is time in milliconds and C RP is capacitance in nanofarads.C RP is charged with a precision current source of 400nA,a high quality,low leakage capacitor (such as an NPO ceramic)should be ud to maintain timing tolerances.Fig.5illustrates the voltage levels and timings associated with the ret circuit.Programming the Watchdog Period
The watchdog period is programmed with C WP as fol-lows:
T C WP WP
=•25where T WP is in milliconds and C WP is in nanofarads.A high quality,low leakage capacitor should be ud for C WP .The watchdog input WDI must be toggled with a high/low or low/high transition within the watchdog period to prevent WDO from assuming a logic level low.WDO will maintain the low logic level until WDI is toggled or RES is asrted.If at any time RES is asrted,WDO will assume a high logic state and the watchdog period will be reinitiated.Fig.6illustrates the timings associated with the watchdog circuit.easytalking
Figure 4.Typical application diagram.
男子的英文名miamiConnecting WDO to RES
In order to provide design flexibility,the ret and watch-dog circuits in the UCC3946have parate outputs.Each output will independently drive high or low,depending on circuit conditions explained previously.
In some applications,it may be desirable for either the RES or WDO to ret the microprocessor.This can be done by connecting WDO to RES.If the pins try to drive to different output levels,the low output level will domi-nate.Additional current will flow from VDD to GND during the states.If the application cannot support additional current(during fault conditions),RES and WDO can be connected to the inputs of an OR gate who output is connected to the microprocessor’s ret pin.Layout Considerations
A0.1µF capacitor connected from V DD to GND is recom-mended to decouple the UCC3946from switching tran-sients on the V DD supply rail.
Since RP and WP are precision current sources,capaci-tors C RP and C WP should be connected to
the pins with minimal trace length to reduce board capacitance. Care should be taken to route any traces with high volt-age potential or high speed digital signals away from the capacitors.
有所裨益Resistors R1and R2generally have a high ohmic value, traces associated with the parts should be kept short in order to prevent any transient producing signals from coupling into the high impedance RTH pin.
散文下载Figure 5.Ret circuit timings.
