Symbol DC Parameter
Conditions
Min Typ Max Units DV PPIN
Differential peak-to-peak input voltage (external AC coupled)
>10.3125Gb/s
150
–1250mV 6.6Gb/s to 10.3125Gb/s 150–1250mV ≤6.6Gb/s 150–2000mV
V IN Single-ended input voltage (1)DC coupled
V MGTAVTT =1.2V –400–V MGTAVTT
mV V CMIN Common mode input voltage
DC coupled
V MGTAVTT =1.2V
–2/3 V MGTAVTT
–mV DV PPOUT Differential peak-to-peak output voltage (2)Transmitter output swing is t to 1010800
–
–
mV V CMOUTDC Common mode output voltage: DC coupled
Equation bad V MGTAVTT –DV PPOUT /4mV V CMOUTAC Common mode output voltage: AC coupled
Equation bad V MGTAVTT –DV PPOUT /2mV
R IN Differential input resistance –100–ΩR OUT Differential output resistance
–100–ΩT OSKEW Transmitter output pair (TXP and TXN) intra-pair skew ––10ps C EXT Recommended external AC coupling capacitor (3)
–
100
–
nF
Notes:
1.Voltage measured at the pin referenced to ground.
2.The output swing and preemphasis levels are programmable using the attributes discusd in the 7Series FPGAs GTX/GTH Transceiver Ur Guide (UG476), and can result in values lower than reported in this table.
3.
Other values can be ud as appropriate to conform to specific protocols and standards.
Figure 6:Single-Ended Peak-to-Peak Voltage
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Note:In Figure 7, differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2.
Table 69 summarizes the DC specifications of the clock input of the GTH transceiver. Consult the 7Series FPGAs GTX/GTH Transceiver Ur Guide (UG476) for further details.
Figure 7:Differential Peak-to-Peak Voltage
Table 69:GTH Transceiver Clock DC Input Level Specification
Symbol DC Parameter
Min Typ Max Units V IDIFF Differential peak-to-peak input voltage
350–2000mV R IN Differential input resistance
–100–
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Required external AC coupling capacitor
–
100
–
nF
Table 74:GTH Transceiver Ur Clock Switching Characteristics (1)
Symbol Description
Data Width Conditions Speed Grade
Units Internal Logic
Interconnect Logic -3E/-2GE (2)
-2(C/I)/-2LE (2)-1(C/I/M)(3)
F TXOUT TXOUTCLK maximum frequency 412.500412.500312.500MHz F RXOUT RXOUTCLK maximum frequency 412.500
412.500312.500MHz F TXIN TXUSRCLK
maximum frequency 16-bit 16-bit and 32-bit 412.500412.500312.500MHz 32-bit 32-bit
409.375353.125265.625MHz F RXIN
RXUSRCLK
maximum frequency 16-bit 16-bit and 32-bit 412.500412.500312.500MHz 32-bit 32-bit 409.375353.125265.625MHz F TXIN2botel
TXUSRCLK2shy
maximum frequency
16-bit
16-bit 412.500412.500312.500MHz 16-bit and 32-bit 32-bit 409.375353.125265.625MHz 32-bit 64-bit 204.688176.563132.813MHz F RXIN2
RXUSRCLK2
maximum frequency
16-bit
16-bit 412.500412.500312.500MHz 16-bit and 32-bit 32-bit 409.375353.125265.625MHz 32-bit
64-bit
204.688
176.563
132.813
MHz
Internal Configuration Access Port F ICAPCK
Internal configuration access port (ICAPE2)
Master SLR ICAP accessing the entire device
70.00
70.00
70.00
MHz, Max
SLR ICAP accessing the local SLR 100.00100.00100.00MHz, Max All other devices
100.00
100.00
100.00
MHz, Max
Master/Slave Serial Mode Programming Switching T DCCK /T CCKD DIN tup/hold 4.0/0.0 4.0/0.0 4.0/0.0ns, Min T CCO
DOUT clock to out
8.0
8.0
8.0
ns, Max
handoff
SelectMAP Mode Programming Switching
T SMDCCK /T SMCCKD D[31:00] tup/hold 4.0/0.0 4.0/0.0 4.0/0.0ns, Min T SMCSCCK /T SMCCKCS CSI_B tup/hold
我无能为力4.0/0.0 4.0/0.0 4.0/0.0ns, Min T SMWCCK /T SMCCKW RDWR_B tup/hold
10.0/0.010.0/0.010.0/0.0ns, Min T SMCKCSO CSO_B clock to out (330Ω pull-up resistor required)7.07.07.0ns, Max T SMCO D[31:00] clock to out in readback 8.08.08.0ns, Max F RBCCK
Readback frequency
SLR-bad N/A 7070MHz, Max All other devices
管子英文
100
100
100
MHz, Max
Boundary-Scan Port Timing Specifications T TAPTCK /T TCKTAP TMS and TDI tup/hold SLR-bad N/A 9.0/2.09.0/2.0ns, Min All other devices 3.0/2.0 3.0/2.0 3.0/2.0ns, Min T TCKTDO TCK falling edge to TDO output SLR-bad N/A 1717ns, Max All other devices 7.07.07.0ns, Max F TCK
TCK frequency
SLR-bad N/A 2020MHz, Max All other devices
66
66
66
MHz, Max
BPI Flash Master Mode Programming Switching T BPICCO (2)A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B clock to out 8.58.58.5ns, Max T BPIDCC /T BPICCD D[15:00] tup/hold
4.0/0.0
4.0/0.0
4.0/0.0
ns, Min
SPI Flash Master Mode Programming Switching
T SPIDCC /T SPICCD D[03:00] tup/hold 3.0/0.0 3.0/0.0 3.0/0.0ns, Min T SPICCM MOSI clock to out 8.08.08.0ns, Max T SPICCFC
FCS_B clock to out
8.0
8.0
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ns, Max
STARTUPE2 Ports T USRCCLKO STARTUPE2 USRCCLKO input to CCLK output 0.50/6.000.50/6.700.50/7.50ns, Min/Max F CFGMCLK STARTUPE2 CFGMCLK output frequency
65.0065.0065.00MHz, Typ F CFGMCLKTOL STARTUPE2 CFGMCLK output frequency tolerance
±50
±50
±50
%, Max
Device DNA Access Port
F DNACK DNA access port (DNA_PORT)
100.00
100.00
100.00
MHz, Max
Notes:
1.To support longer delays in configuration, u the design solutions described in the 7Series FPGA Configuration Ur Guide (UG470).新概念英语1
2.
Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
Table 85:Configuration Switching Characteristics (Cont’d)
兰花英文Symbol
Description
Virtex-7T and XT
Devices
Speed Grade Units
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-2/-2L/-2G
-1/-1M
