■On-chip ries termination without calibration ■On-chip parallel termination with calibration (OCT R T )■On-chip differential termination (OCT R D )■
PCI clamping diode
The I/O registers are compod of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output-enable (OE) path for handling the OE signal for the output buffer. The registers allow faster source-synchronous register-to-register transfers and resynchronization. The input path consists of the DDR input registers, alignment and synchronization registers, and HDR. You can bypass each block of the input path. Figure 7–7 shows the Stratix III IOE structure.
The output and OE paths are divided into output or OE registers, alignment registers, and HDR blocks. You can bypass each block of the output and OE path.
f
For more information about I/O registers and how they are ud for memory applications, refer to the External Memory Interfaces in Stratix III Devices chapter.
Figure 7–7.IOE Structure for Stratix III Devices (Note 1), (2)
Notes to Figure 7–7:
(1)D3_0 and D3_1 delays have the same available ttings in the Quartus ®II software. (2)One dynamic OCT control is available per DQ/DQS group.
窘态OE
from Core
Data from Core
To Core To Core
clkin
Data to Core
DQS CQn
Chapter 7:Stratix III Device I/O Features
Stratix III I/O Structure
Stratix III I/O Structure
Programmable Differential Output Voltage
Stratix III LVDS transmitters support programmable V OD . The programmable V OD ttings enable you to adjust output eye height to optimize for trace length and power consumption. A higher V OD swing improves voltage margins at the receiver end while a smaller V OD swing reduces power consumption. The Quartus II software allows four ttings for programmable V OD —low, medium low, medium high, and high. The default tting is medium low.
f
For more information about programmable V OD , refer to the High Speed Differential I/O Interfaces with DPA in the Stratix III Devices chapter.
MultiVolt I/O Interface
The Stratix III architecture supports the MultiV olt TM I/O interface feature that allows Stratix III devices in all packages to interface with systems of different supply voltages.
You can connect the V CCIO pins to a 1.2-, 1.5-, 1.8-, 2.5-, 3.0 or 3.3-V power supply , depending on the output requirements. The output levels are compatible with
systems of the same voltage as the power supply. (For example, when V CCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems.)
You must connect the Stratix III VCCPD power pins to a 2.5-, 3.0 or 3.3-V power supply . Using the power pins to supply the pre-driver power to the output buffers increas the performance of the output pins. Table 7–7 summarizes Stratix III MultiV olt I/O support. 1
For V CCIO = 3.3 V , V CCPD =3.3 V . For V CCIO = 3.0 V , V CCPD = 3.0 V . For V CCIO = 2.5 V or less, V CCPD = 2.5 V .
Table 7–7.MultiVolt I/O Support for Stratix III Devices (Note 1), (2)
Notes to Table 7–7:
(1)The pin current may be slightly higher than the default value. You must verify that the driving device’s V OL maximum and V OH minimum voltages
do not violate the applicable Stratix III V IL maximum and V IH minimum voltage specifications.
(2)U on-chip PCI clamp diode for column I/Os or external PCI clamp diode for row I/Os to protect the input pins against overshoot voltage.(3)Each I/O bank of a Stratix III device has its own VCCIO pins and supports only one V ccio , either 1.2, 1.5, 1.8, or 3.0V. The LVDS I/O standard
requires that a V CCIO of 2.5V cannot be assigned in a same bank with a 3.0-V or 3.3-V output signal.
OCT Support
Dynamic OCT
Stratix III devices support on-off dynamic ries and parallel termination for a
bi-directional I/O in all I/O banks. Figure7–11 shows the termination schemes
supported in the Stratix III device. Dynamic parallel termination is enabled only
when the bi-directional I/O acts as a receiver and is disabled when it acts as a driver.
Similarly, dynamic ries termination is enabled only when the bi-directional I/O acts
arafesas a driver and is disabled when it acts as a receiver. This feature is uful for
terminating any high-performance bi-directional path becau the signal integrity is
optimized depending on the direction of the data.
You should connect a bi-directional pin that us both 25-Ω or 50-Ω ries termination
and 50-Ω input termination to a calibration block that has a 50-Ω external resistor
connected to its RUP and RDN pins. The 25-Ω ries termination on the bi-directional
pin is achieved through internal divide by two circuits.受尊重
Figure7–11.Dynamic Parallel OCT in Stratix III Devices
翻译学院
f For more information about tolerance specifications for OCT with calibration, refer to
the DC and Switching Characteristics of Stratix III Devices chapter.
Chapter 7:Stratix III Device I/O Features
OCT Support
LVDS Input On-Chip Termination (R
D
)
Stratix III devices support OCT for differential LVDS input buffers with a nominal
resistance value of 10Ω, as shown in Figure7–12. You can enable OCT R
D
体裁
in row I/O
banks when V
CCIO and V
CCPD
are t to 2.5V. The column I/O banks do not support
OCT R
D.
The dedicated clock input pairs CLK[1,3,8,10][p,n],
PLL_L[1,4]_CLK[p,n], and PLL_R[1,4]_CLK[p,n] on the row I/O banks of the
Stratix III devices do not support OCT R
focusframeD
. Dedicated clock input pairs
fight togetherCLK[0,2,9,11][p,n] on row I/O banks support OCT R
D
ato. Dedicated clock input pairs CLK[4,5,6,7][p,n] and CLK[12,13,14,15][p,n] on column I/O banks do not
bsts
support OCT R
D
.
f For more information about OCT R
D
, refer to the High Speed Differential I/O Interfaces with DPA in Stratix III Devices chapter.
Table7–11 lists the assignment name and its value for OCT R
D
in the Quartus II software Assignment Editor.
1You must t the V
CCIO to 2.5V when OCT R
D
is ud for the LVDS input buffer, even if
the LVDS input buffer is powered by V
CCPD .
Figure7–12.Differential Input On-Chip Termination
暑假培训班Table7–11.On-Chip Differential Termination in Quartus II Software Assignment Editor
