K9GBGD8XXM_0.4_Enterpri

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K9GBGD8X0M K9LCGD8X1M K9HDGD8X5M K9PFGD8X7M K9PFGD8X5M

hotchineDocument Title

Samsung Toggle Mode DDR NAND Specification Revision History

英语辅导报网站The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. rerve

the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, plea contact the SAMSUNG branch office near your office.

Revision No

0.00.10.1.5

0.20.30.4Remark

Advance

History 1. Initial issue

1. Restriction of Command latch cycle is noted.

2. Output driver strength impedence values for VccQ=1.8V is added.1. K9LCGD8U1M-B, K9LCGD8S1M-B are added.2. K9HDGD8U5M-B, K9HDGD8S5M-B are added.

3. K9PFGD8U7M-B, K9PFGD8S7M-B are added.

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4. Ball pitch is changed from 1.4mm to 1.0mm.

1. Package type is changed from 100FBGA t o 180FBGA.

2. Output Driver Strength Values are changed.

3. Note 1 of 5.16 is amended. (Icc1 30mA -> 50mA)1. Max. tR is changed from 400us to 80us.2. Typ. tPROG is changed from 1.6ms to 2ms.

1. K9PFGD8U5M-B, K9PFGD8S5M-B are added.

2. Package dimension is amended.

3. Chip2 Status command(F2h) is added for K9PFGD8X5M.

4. Functional block diagram is modified.

5. A 34 is added for K9PFGD8X5M.

6. Absolute maximum ratings are noted for each VccQ.

7. Stand-by current of TTL(I SB1) is deleted.

8. Test conditions of Output High and Low Voltage Level are noted.9. Min. valid blocks of all products are amended.10. tR is noted for typical and maximum value.sweet是什么意思中文

11. Device retting time of Era is changed from 500us to 100us.

12. Timing of Status Read Cycle before Power On quence is described.13. Device ID of K9PFGD8X5M is added.14. Device ID table definitions is amended.15. Get feature command is deleted.

16. Busy time for Set and Get feature(tFEAT) is deleted.

17. Timing diagram of Driver Strength Register Setting is amended.18. Interleaving operations for K9PFGD8X5M are added.

Draft Date

May 26, 2009Jun. 15, 2009Jul. 14, 2009

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Sep. 24, 2009

Oct. 22 , 2009

1.0 Introduction

1.1 GENERAL DESCRIPTION

stephanie pratt

Offered in 4Gx8bit, the K9GBGD8X0M is a 32G-bit NAND Flash Memory with spare 2,076M-bit. The device is offered in 3.3V Vcc & VccQ.

(3.3V & 1.8V) and also us the toggle mode interface to achieve a high data transfer rate. Its NAND

cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 2ms on the (8K+512)Byte page and an era operation can be performed in typical 1.5ms on a (1M+64K)Byte block. Data in the data register can be read out at 133Mbps with 15ns cycle time. The I/O pins rve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and era functions including pul repetition, where required, and internal verification and margining of data. The K9GBGD8X0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

1.2 FEATURES

• Voltage Supply :

- Core : 2.7V ~ 3.6V

- I/O : 2.7V ~ 3.6V / 1.7V ~ 1.95V

• Organization

- Memory Cell Array : (4G + 259.5M) x 8bit

- Data Register : (8K + 512) x 8bit

• Automatic Program and Era

- Page Program : (8K + 512)Byte

- Block Era : (1M + 64K)Byte

• Page Read Operation

- Page Size : (8K + 512)Byte

- Random Read : 80µs(Typ.) , 100µs(Max.)

- Data Transfer rate : 133Mbps(VccQ:3.3V) / 66Mbps(VccQ:1.8V)• Fast Write Cycle Time

- Page Program time : 2ms(Typ.)

英语六级考试时间安排- Block Era Time : 1.5ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Toggle Mode DDR Data Interface • Hardware Data Protection

- Program/Era Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- ECC Requirement : 24bits/1Kbyte

- Endurance & Data Retention : Plea refer to the Qualification report

• Command Driven Operation

• Scalable I/O Driver

• Package

- K9GBGD8U0M-BCB0: Pb/Halogen Free Package