module adder4(cout,sum,ina,inb,cin);
output[3:0] sum;
output cout;london olympic
input[3:0] ina,inb;
input cin;
assign {cout,sum}=ina+inb+cin;
endmodule
【例3.2】4位计数器电影后天
module count4(out,ret,clk);
output[3:0] out;
input ret,clk;
reg[3:0] out;
always @(podge clk)
begin
if (ret) out<=0; //同步复位
el out<=out+1; //计数
end
ontheotherhand
endmodule
【例3.3】4位全加器的仿真程序
`timescale 1ns/1ns
`include "adder4.v"
module adder_tp; //测试模块的名字
reg[3:0] a,b; //测试输入信号定义为reg型reg cin;
wire[3:0] sum; //测试输出信号定义为wire型wire cout;
integer i,j;
adder4 adder(sum,cout,a,b,cin); //调用测试对象
always #5 cin=~cin; //设定cin的取值
initial
begin
a=0;b=0;cin=0;
for(i=1;i<16;i=i+1)
#10 a=i; //设定a的取值
end
initial
begin
for(j=1;j<16;j=j+1)
#10 b=j; //设定b的取值
end
initial//定义结果显示格式
begin
$monitor($time,,,"%d + %d + %b={%b,%d}",a,b,cin,cout,sum);
#160 $finish;
end
kgs
endmodule
【例3.4】4位计数器的仿真程序
`timescale 1ns/1ns
`include "count4.v"
module coun4_tp;
reg clk,ret; //测试输入信号定义为reg型
wire[3:0] out; //测试输出信号定义为wire型parameter DELY=100;
count4 mycount(out,ret,clk); //调用测试对象
always #(DELY/2) clk = ~clk; //产生时钟波形
initial
begin//激励信号定义
clk =0; ret=0;
#DELY ret=1;
#DELY ret=0;
#(DELY*20) $finish;
end
//定义结果显示格式
initial $monitor($time,,,"clk=%d ret=%d out=%d", clk, ret,out); endmodule
【例3.5】“与-或-非”门电路
module AOI(A,B,C,D,F); //模块名为AOI(端口列表A，B，C，D，F) input A,B,C,D; //模块的输入端口为A，B，C，D
output F; //模块的输出端口为F
wire A,B,C,D,F; //定义信号的数据类型assign F= ~((A&B)|(C&D)); //逻辑功能描述
endmodule
【例5.1】用ca语句描述的4选1数据选择器ankle什么意思
module mux4_1(out,in0,in1,in2,in3,l);
output out;
input in0,in1,in2,in3;
input[1:0] l;
pearl harborreg out;
always @(in0 or in1 or in2 or in3 or l) //敏感信号列表ca(l)
2'b00: out=in0;
2'b01: out=in1;
2'b10: out=in2;
2'b11: out=in3;
default: out=2'bx;
endca
圣诞老人 英语endmodule
【例5.2】同步置数、同步清零的计数器
module count(out,data,load,ret,clk);
output[7:0] out;
input[7:0] data;
input load,clk,ret;
reg[7:0] out;
always @(podge clk) //clk上升沿触发begin
if (!ret) out = 8'h00; //同步清0，低电平有效el if (load) out = data; //同步预置
el out = out + 1; //计数
end
endmodule
【例5.3】用always过程语句描述的简单算术逻辑单元
`define add 3'd0
`define minus 3'd1
`define band 3'd2
`define bor 3'd3
`define bnot 3'd4
module alu(out,opcode,a,b);
output[7:0] out;
reg[7:0] out;
input[2:0] opcode; //操作码
初三英语作文input[7:0] a,b; //操作数
always@(opcode or a or b) //电平敏感的always块begin
ca(opcode)
`add: out = a+b; //加操作
`minus: out = a-b; //减操作
`band: out = a&b; //求与
`bor: out = a|b; //求或
`bnot: out=~a; //求反
default: out=8'hx; //未收到指令时，输出任意态endca
end
endmodule
【例5.4】用initial过程语句对测试变量A、B、C赋值
`timescale 1ns/1ns
module test;
reg A,B,C;
initial
电子词典
begin
A = 0;
B = 1;
C = 0;
#50 A = 1; B = 0;
#50 A = 0; C = 1;
coca cola#50 B = 1;
#50 B = 0; C = 0;
#50 $finish ;
end
endmodule
【例5.5】用begin-end串行块产生信号波形
`timescale 10ns/1ns
module wave1;
reg wave;
parameter cycle=10;
initial
begin
wave=0;
#(cycle/2) wave=1;
#(cycle/2) wave=0;
#(cycle/2) wave=1;
#(cycle/2) wave=0;
#(cycle/2) wave=1;
#(cycle/2) $finish ;
end
initial $monitor($time,,,"wave=%b",wave); endmodule
【例5.6】用fork-join并行块产生信号波形
`timescale 10ns/1ns
module wave2;
reg wave;
parameter cycle=5;
initial
fork
wave=0;
#(cycle) wave=1;
#(2*cycle) wave=0;
#(3*cycle) wave=1;
#(4*cycle) wave=0;
#(5*cycle) wave=1;
#(6*cycle) $finish;
join
initial $monitor($time,,,"wave=%b",wave); endmodule
【例5.7】持续赋值方式定义的2选1多路选择器
module MUX21_1(out,a,b,l);
input a,b,l;
output out;
assign out=(l==0)?a:b;
//持续赋值，如果l为0，则out=a ；否则out=b endmodule
【例5.8】阻塞赋值方式定义的2选1多路选择器
module MUX21_2(out,a,b,l);
input a,b,l;
