AES_128加密解密算法,verilog实现。完整代码具体的理论知识，本⼈不在详述。⽹上已经有很多了
以上内容都对aes_128加密有很详细的说明。
下⾯直接进⼊正题，代码实现！
⼀、top层模
详细说明已在模块内部标注
1/*
2说明：
3 1.aes_top模块作⽤是完成整个加密或者解密轮循环的计数，及对应的数据流向。
4 2.由于加解密10轮循环不是完全⼀样的，所有需设计状态机4种状态，初始状态，开始状态，中间9轮
5轮循环计数状态及最后⼀轮状态。
6 3.密钥扩展可以在循环之前把⼗轮密钥全部计算存⼊寄存器组，也可以在每轮循环中做⼀次密钥扩展，
7由于节省资源，本⼈是在每次轮循环时，再计算密钥扩展。
8
9
10*/
11module aes_top(
12 input clk,
13 input rst_n,
14 input start_i, //加解密开始信号
15 input decrypt, //加密 / 解密
16 input [127:0] data_in, // 密⽂输⼊
17 input [127:0] key_in, // 密钥输⼊
18 output reg [127:0] data_o, // 明⽂
19 output reg ready_o //完成标志信号
20);
21//状态参数
22 localparam IDLE =4'b0001,
23 FIRST =4'b0010,
24 MIDDLE =4'b0100,
25 FINALLY=4'b1000;
26 reg [3:0] state;
27 reg [3:0] state_next;
28 wire idle_first ;
29 wire first_middle ;
30 wire middle_finally ;
31 wire finally_idle ;
32
33//计数器
34 reg [3:0] cnt;
35 wire add_cnt;
36 wire end_cnt;
37 reg decrypt_i; //加解密寄存器
38 wire midround_done;
39 reg first_round;
40 reg finally_end;
41
42
43
44//密钥寄存器组
45 reg [127:0] key_orginal ;
46 reg [3:0] rcon ;
47 reg key_en ;snack
48 wire key_done ;
49 wire [127:0] key_rdata ;
50
51 //列混合变量
52 reg mixcolum_en ;
52 reg mixcolum_en ;
53 wire [127:0] mixcolum_data ;
54 wire [127:0] mixcolum_dout ;
55 wire mixcolum_ready ;
56//⾏移位变量
57 reg invshiftrow_en ;
58 reg [127:0] invshiftrow_data ;
59 wire [127:0] invshiftrow_dout ;
60 wire invshiftrow_ready ;
61//字节代换变量
62 wire sbox_ready ;
63 wire [127:0] sbox_dout ;
64 reg sbox_en ;
65 wire [127:0] sbox_data ;
66//轮密钥加变量
67 reg addround_flag2;
68 reg addround_flag1;
69 reg addround_en1 ;
70 wire addround_en ;
71 reg [127:0] addround_data ;
72 wire [127:0] addround_key ;
73 wire [127:0] addround_dout ;
74 wire addround_ready ;
75
76//******************************************************************/
77
78 //decrypt 打拍，也可不⽤打拍
79 always @(podge clk or negedge rst_n) begin
80 if(!rst_n) begin
81 decrypt_i <= 0;
82 end
83 el begin
84 decrypt_i <= decrypt;
85 end
86 end
87
88
89 //中间9轮计数
90 always @(podge clk or negedge rst_n) begin
91 if(!rst_n) begin
92 cnt <= 0;
93 end
94 el if(add_cnt) begin
95 if(end_cnt) begin
96 cnt <= 0;
97 end
98 el begin
99 cnt <= cnt + 1'b1 ;
100 end
101 end
102 end
103
104 assign add_cnt = (state==MIDDLE) && midround_done ;
105 assign end_cnt = add_cnt && (cnt==9-1);
106 assign midround_done = (decrypt_i ? mixcolum_ready : addround_ready); 107
108 always@(podge clk or negedge rst_n) begin
109 if(!rst_n) begin
110 state <= IDLE;
111 end
112 el begin
113 state <= state_next;
114 end
115 end
116 always @(*) begin
117 ca (state)
117 ca (state)
118 IDLE :begin
119 if(idle_first) begin
120 state_next = FIRST;
121 end
122 el begin
123 state_next = IDLE;turn over
124 end
125 end
126 FIRST :begin
127 if(first_middle) begin
128 state_next = MIDDLE;
129 end
130 el begin
131 state_next = FIRST;
132 end
133 end
134 MIDDLE :begin
135 if(middle_finally) begin
136 state_next = FINALLY;
137 end
indicates
138 el begin
how deep is your love
139 state_next = MIDDLE;
140 end
141 end
142 FINALLY :begin
143 if(finally_idle) begin
144 state_next = IDLE;
145 end
146 el begin
147 state_next = FINALLY;
148 end
149 end
150 default:state_next = IDLE;
151 endca
152 end
153 assign idle_first = state==IDLE && (start_i ) ; //IDLE初始状态
154 assign first_middle = state==FIRST && (first_round ) ; //第⼀次轮密钥加155 assign middle_finally = state==MIDDLE && (end_cnt ) ; //中间循环9次156 assign finally_idle = state==FINALLY && (finally_end ) ; //最后⼀次循环157
158
159 always@(podge clk or negedge rst_n) begin
160 if(!rst_n) begin
161 first_round <= 0;
162 end
163 el if(state==FIRST) begin
164 first_round <= addround_ready ;
165 end
166 el begin
167 first_round <= 0;
168 end
169 end
170 always@(podge clk or negedge rst_n) begin
171 if(!rst_n) begin
172 finally_end <= 0;
173 end
174 el if(state==FINALLY) begin
175 finally_end <= addround_ready ;
176 end
177 el begin
178 finally_end <= 0;
179 end
180 end
181
182
182
183//密钥扩展
184 key_memory u_key_memory(
185 //exterior
186 .clk (clk ),
187 .rst_n (rst_n ),
188 .start_i (key_en ),
189 .key_in (key_orginal ),
190 .rcon (rcon ), //轮常量
191 .key_rcon (key_rdata ),
192 .allkey_done (key_done )
193 );
194
195 //key_orginalroadtrip
196 always@(podge clk or negedge rst_n) begin
taste怎么读197 if(!rst_n) begin
198 key_orginal <= 0;
199 end
200 el if(start_i) begin
201 key_orginal <= key_in ;
202 end
203 end
204 //rcon 轮常量计数
205 always@(podge clk or negedge rst_n) begin
206 if(!rst_n) begin
207 rcon <= 0;
208 end
209 el if( ~decrypt_i ) begin
210 if(state==FIRST || state==IDLE) begin
211 rcon <= 0;
212 end
213 el if(state==MIDDLE) begin //正向加密不需要等所有密钥扩展完，即可加密；214 ca(cnt) //逆向解密必须要等所有密钥扩展完，才能加密
215 0: rcon <= 1;
216 1: rcon <= 2;
217 2: rcon <= 3;
218 3: rcon <= 4;the的用法
219 4: rcon <= 5;
220 5: rcon <= 6;
221 6: rcon <= 7;
222 7: rcon <= 8;
223 8: rcon <= 9;
224 default:;
225 endca
226 end
227 el if(state==FINALLY) begin
228 rcon <= 10;
229 end
230 end
231 el if(decrypt_i) begin
232 if(state==FIRST || state==IDLE) begin
233 rcon <= 10;
cockroach234 end
235 el if(state==MIDDLE) begin
236 ca(cnt)
237 0: rcon <= 9;
238 1: rcon <= 8;
239 2: rcon <= 7;
240 3: rcon <= 6;
241 4: rcon <= 5;
242 5: rcon <= 4;
243 6: rcon <= 3;
244 7: rcon <= 2;
245 8: rcon <= 1;
246 default:rcon <= 0;
247 endca
247 endca
248 end
249 el if(state==FINALLY) begin
250 rcon <= 0;
251 end
252 end
253 end
254 //key_en 需在字节代换后，开始计算密钥
255 always @(podge clk or negedge rst_n) begin 256 if(!rst_n) begin
257 key_en <= 0;
258 end
259 el begin
260 key_en <= sbox_ready | start_i;
261 end
262 end
263
264
265
266 addroundkey u_add( //轮密钥加
267 .clk (clk ) ,
268 .rst_n (rst_n ) ,
269 .start_i (addround_en ) ,
270 .data (addround_data ) ,
271 .key (addround_key ) ,
272
273 .data_o (addround_dout ) ,
274 .ready_o (addround_ready)
275 );
276
277 //轮密钥加循环条件转换
278 assign addround_key = key_rdata ;
279 always @(podge clk or negedge rst_n) begin 280 if(!rst_n) begin
281 addround_en1 <= 0;zho
282 addround_data <= 0;
283 // addround_key <= 0;
284 end
285 el if(state==MIDDLE )begin
286 if(~decrypt_i) begin
287 addround_en1 <= mixcolum_ready ; 288 addround_data <= mixcolum_dout;
289
290 //addround_key <= key_rdata;
291 end
292 el begin
293 addround_data <= sbox_dout ;
294 addround_en1 <= sbox_ready ;
295
296 //addround_key <= key_rdata;
297 end
298 end
dragon boat festival299 el if(state==FINALLY )begin
300 if(~decrypt_i) begin
301 addround_en1 <= invshiftrow_ready ; 302 addround_data <= invshiftrow_dout ; 303
304 // addround_key <= key_rdata;
305 end
306 el begin
307 addround_data <= sbox_dout ;
308 addround_en1 <= sbox_ready ;
309
310 //addround_key <= key_rdata;
311 end
312 end
