【Verilog】基于FPGA的打地⿏⼩游戏设计（VGA显⽰、附代码、演⽰视频）基于FPGA的打地⿏⼩游戏设计
1、⼀个.v⽂件，便于读者理解和使⽤；
2、游戏思路相关说明：
VGA显⽰九宫格（地⿏洞⽳）
绿⾊⾊块（地⿏）、击中地⿏（⾊块变红）
可调地⿏数量和地⿏出现速度
倒计时⾄零或数量达关卡⽬标即游戏结束；
3、使⽤资源：板载的5个按键、⼀个⽤于复位的拨码开关；
4、阿汪先⽣⽤的板⼦型号为：xc7a35tcsg324-1 。
下列所有代码可直接在各FPGA板上运⾏
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2019/05/21 09:48:34
// Design Name:
// Module Name: VGA00
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
/
/
笼罩的拼音// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module VGA(clock,switch,disp_RGB,hsync,vsync,up,down,left,right,middle,rst ,QC_OUT,QA_OUT,led);
input clock; //系统输⼊时钟100MHz
input[1:0]switch;
input rst;
output [7:0] QC_OUT;
output[3:0] QA_OUT;
output [7:0] led;
input up,down,left,right,middle;
output[11:0]disp_RGB;//VGA数据输出
output hsync;//VGA⾏同步信号
output vsync;//VGA场同步信号
reg [9:0] hcount; //VGA⾏扫描计数器
reg [9:0] vcount; //VGA场扫描计数器
reg [11:0] data;
reg [11:0] h_dat;
reg [11:0] v_dat;
reg [11:0] x_dat;
reg [11:0] data1;
reg [11:0] data1;
reg flag=0;
wire hcount_ov;
wire vcount_ov;
wire dat_act;
wire hsync;
wire vsync;
reg background=12'b010*********; reg gezi=12'b010********;
reg jieshu=12'hf00;
reg vga_clk=0;
reg cnt_clk=0;//分频计数
always@(podge clock)
begin
if(cnt_clk==1)begin
vga_clk<=~vga_clk;
cnt_clk<=0;
end
el
cnt_clk<=cnt_clk+1;
endhavedinner
//***************VGA驱动部分*****************8// //⾏扫描
// VGA⾏、场扫描时序参数表parameter hsync_end =10'd95,
hdat_begin=10'd143,
hdat_end=10'd783,
hpixel_end=10'd799,
vsync_end=10'd1,
vdat_begin =10'd34,
vdat_end=10'd514,
vline_end=10'd524;
always@(podge clock)
begin
if(cnt_clk==1)begin
vga_clk<=~vga_clk;
cnt_clk<=0;
end
el
cnt_clk<=cnt_clk+1;
end
//***************VGA驱动部分*****************8// //⾏扫描pervert
治疗青春痘方法always@(podge vga_clk)
begin
if(hcount_ov)
hcount<=10'd0;
el
hcount <= hcount + 10'd1;
end
assign hcount_ov =(hcount==hpixel_end);
//场扫描
always@(podge vga_clk)
begin
if(hcount_ov)
begin
if(vcount_ov)
vcount<=10'd0;
el
vcount<=vcount+10'd1;
vcount<=vcount+10'd1;
end
end
assign vcount_ov=(vcount==vline_end);
//数据、同步信号
assign dat_act=((hcount>=hdat_begin)&&(hcount<hdat_end))&&((vcount>=vdat_begin)&&(vcount<vdat_end)); assign hsync=(hcount>hsync_end);
assign vsync=(vcount>vsync_end);
assign disp_RGB=(dat_act)?data:12'h00;
//显⽰图像
/* always@(podge vga_clk)
begin
ca(switch[1:0])
2'd0:data<=h_dat;
2'd1:data<=v_dat;
2'd2:data<=h_dat&v_dat;
2'd3:data<=x_dat&h_dat&v_dat;
endca;
end */
//计时1秒
reg [28:0]jishu_1s=0;
reg clk_1s=0;
localparam tick=50000000;
always @ (podge clock)
begin
ytd
if(jishu_1s==tick)
begin
jishu_1s<=0;
clk_1s=~clk_1s;
end
el
begin
jishu_1s<=jishu_1s+1;
end
end
//计时50ms
reg clk_50ms=0;
耸立是什么意思localparam DVSR=5000000;
reg [28:0] js;
always @ (podge clock)
begin
if(js==DVSR)
begin
js<=0;
clk_50ms=~clk_50ms;
end
el
begin
js<=js+1;
end
end
/
/产⽣竖长条
always@(podge vga_clk)
discuss的过去式begin
if(hcount<=220||hcount>=620)
v_dat <= 12'h000;//hei
el if(hcount==240 ||hcount ==360||hcount ==480||hcount==600)
v_dat <= 12'h000;//hei
el
el
v_dat <= 12'hfff;//bai
end
/
/产⽣横长条
always@(podge vga_clk)
begin
if(vcount<=70||vcount>=470)
h_dat <= 12'h000;//hei
el if(vcount==90 ||vcount ==210||vcount ==330||vcount ==450) h_dat <= 12'h000;
el
h_dat <= 12'hfff; //背景
end
parameter WIDTH = 60, //矩形长
HEIGHT = 60, //矩形宽
/
/显⽰区域的边界
DISV_TOP = 10'd120,
DISV_DOWN =DISV_TOP+HEIGHT,
DISH_LEFT = 10'd270,
DISH_RIGHT = DISH_LEFT + WIDTH;
//初始矩形的位置，在显⽰区的左下⾓
reg [9:0] topbound =DISV_TOP;
reg [9:0] downbound ;
reg [9:0] leftbound = DISH_LEFT ;
reg [9:0] rightbound ;
reg [2:0] weizhi=0;
/
/5个位置信息
always@(podge clk_50ms)
begin
ca(weizhi[2:0])
3'b000:begin
leftbound<=10'd390; //上
topbound<=10'd120;
end
3'b001:begin
leftbound<=10'd270;
topbound<=10'd240; //左
end
3'b010: begin
leftbound<=10'd390;
topbound<=10'd240; //中
end
3'b011: begin
leftbound<=10'd510;
topbound<=10'd240; //右
end
3'b100: begin
leftbound<=10'd390;
topbound<=10'd360; //下
end
endca
end
reg flag_on=0;
tourmaline//按键位置与屏幕上地⿏位置相同，则改变屏幕上地⿏⾊块的颜⾊
always @(podge clk_50ms) begin
英语新词if( up==1 && weizhi==0 )begin
flag<=1;
// flag_on<=1;
// flag_on<=1;
end
el if( left==1 && weizhi==1 )begin flag<=1;
// flag_on<=1;
end
el if( middle==1 && weizhi==2 )begin flag<=1;
// flag_on<=1;
end
el if( right==1 && weizhi==3 )begin flag<=1;
flag_on<=1;
end
el if( down==1 && weizhi==4 )begin flag<=1;
/
/ flag_on<=1;
end
el begin
flag<=0;
// flag_on<=0;
end
end
//4位数码管显⽰部分的变量定义
reg [7:0] Q1;
reg [7:0] Q2;
reg [7:0] Q3;
reg [7:0] Q4;
reg [7:0] Q;
reg [7:0] Q_OUT;
reg [5:0] i=0;
//每过2秒⾊块换⼀个位置
//20位的伪随机数
wire [7:0] position[0:19];
assign position[0]=0;
assign position[1]=4;
assign position[2]=2;
assign position[3]=1;
assign position[4]=3;
assign position[5]=0;
assign position[6]=4;
assign position[7]=1;
assign position[8]=2;
assign position[9]=4;
assign position[10]=0;
pond是什么意思
assign position[11]=2;
assign position[12]=1;
assign position[13]=3;
assign position[14]=1;
assign position[15]=0;
assign position[16]=3;
assign position[17]=2;
assign position[18]=1;
assign position[19]=4;
reg [11:0]data2=12'h652;
reg count_20=0;
reg [5:0]num=0;
reg [5:0]num1=0;
reg [5:0]cnt_30ss=30;
reg flag_kaishi=0;
reg flag_jieshu=0;
