A Study on Process Integration of High
Voltage BCDMOS IC
Abstract
HV-BCDMOS-IC is a sort of complex circuit compod of Bipolar, CMOS and
LDMOS devices. In this paper, a 600V RESURF LDMOS with a p-type buried
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layer and the metal field plate is propod for improving the surface electric
field and reducing the on-resistance of LDMOS. A 600V BCD technology bad
on standard Bi-CMOS process is realized by adding PN isolation, double well
and other optimized process. With the process simulator TSUPREM-4 and 2-D
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device simulator MEDICI, the process and structures of different devices have
been simulated and optimized, especially for the HV-LDMOS. Using this
i tools
technology we developed a power IC. The test results show a good consistency
with that we have expected. The 600V BCD technology thus can be ud in the
design of HVIC.
hauteKeywords: BCD technology; RESURF; LDMOS; Field Plate
1Introduction
The rapidly growing market of monolithic smart power IC’s (SPIC) greatly accelerates the evolution of BCD technology. Today’s smart power applications require IC control devices in the 50-1200V range. The technologies combine Bipolar, CMOS and power DMOS devices on a single chip. Compared with the traditional bipolar power technology, BCD technology has an obvious advantage. The designers of the BCD have more spaces to choo among high density and low power consumption of CMOS, high power drive capability and high speed of bipolar and large current and high breakdown voltage of DMOS [1]-[5]. A great many rearches have been done by rearchers both at home and abroad [6]-[11]. Now the rearch direction is along high voltage, high power and high density. As for high voltage, the key problem is the design of DMOS device and the process of i
ntegrating it with low voltage devices. The BCD technology abroad has already been very mature, but little rearch work has been done at home. In order to fill such vacancies, we conducted this investigation.
In this paper, the RESURF-LDMOS with lateral double diffud structure, p-type buried layer and metal field plate was propod to achieve the demand of integration on HVIC. Rearch was mainly on the choosing of materials, adjusting of impurity concentration, controlling of thekline
depth of the junctions, and the optimizing of the structure of HV devices. Bad on the rearch of 600V LDMOS, a new process that can integrate the LDMOS with standard Bi-CMOS has been developed. PN isolation, double well and other optimized procesd have also been ud. The experimental results show that this technology can be ud in the design of HVIC.
2The optimization of structure on HV-LDMOS
2.1The stru cture of LDMOS
LDMOS is a lateral power device with double diffud structure. The channel length is decided by the length of the double lateral diffud region. Figure 1 displays the LDMOS device cross ction int
roduced in this study. This device differs from a traditional NMOS device in that it has an extended drain region under field oxide (FOX) consisting of an n-drift region and an n-layer for on-resistance control. This extended drain region supports the high voltages applied to this device. The poly silicon gate extends over a thin gate oxide and the body (p-body) terminating on the FOX. Key LDMOS performance parameters are low on
R and high drain breakdown voltage. Critical LDMOS I-D layout parameters are the distances from source to FOX edge and FOX width, since the distances must sustain the high LDMOS drain voltages.
2.2D e s i gn o f H V-L DM OS
Becau of the affection to the curvature in PN junction interface, the electric field in the surface tends to be larger than the maximum electric field in the body .and the breakdown voltage is decided by the surface breakdown. Meanwhile, when the impact ionization happens, the hot carriers generated in the ionization are apt to enter the silicon oxide layer and become fixed charges which will affect the distribution of the electric field, cau instability to the device and reduce the device reliability. Therefore, for this design, not only the material and structure parameters should be chon properly to bear the breakdown voltage in a given voltage, but also some special structures should be introduced to reduce the maximum surface electric field. This design was bad on the RESURF [12] theory including the buried layer and the field plate [13]-[14] techniques.
2.2.1 Influence on brea kdown voltage by drift r eg io n do s e an d bu r ie d la y e r RESURF (Reduced-Surface-Field) has been extensively ud in the design of High Voltage devices. The key function of it is to reduce the surface electric field by interactions of the electric fields between epitaxial layer depletion region and substrate depletion region. Thus the breakdown point will transfer from surface to the body. When the two breakdowns happen, the device will get its maximum breakdown voltage. As a result, the breakdown voltage of the device is improved. Accordi
ng to this rule, in order to get its maximum breakdown voltage, the drift layer must be fully depleted, and the breakdown point must be in the PN junction interface of the P-substrate and the N-drift layer [15] (A in Figure 1).
The main factors that affect the breakdown voltage are the length of the drift region (d L ), the junction depth and the impurity concentration (d N ). Generally speaking, as the drift region length grows, the lateral breakdown voltage will increa. But when the length grows to a certain value, the lateral breakdown voltage remains constant. The deeper the drift region is, the higher the longitudinal breakdown voltage becomes. An analysis will be made between the drift region do and the breakdown voltage in the following.
The relation between the drift do and breakdown characteristic has been obtained by 2D devices simulator MEDICI. And the result shows when the drift do is too small, the breakdown voltage will be low, which is induced by the surface breakdown in the drain. When the drift do is too large, the breakdown voltage will still stay low, which is ascribed to the avalanche breakdown in the PN junction between the channel and the drift region. As a result, too small or too large a drift do will both do harm to the breakdown voltage. So a compromi do should be included. According to the miconductor device theory, we have the following equations [16],
V N N q N N W a d a d s sub drift )
()(2+=ε (1) )(2)(2a d s sub drift
a d N N W N N q V +=ε (2)
Where drift W is the width of the depletion region of the drift substrate PN junction,d N is the concentration of the n-drift region and a N the concentration of the p-type substrate. V is the backward voltage .
For abrupt junction (such as drift /well junction), the breakdown voltage (BV) is,
d c
s drift well
c qN E W E BV 222ε== (3)
Where c E is the critical electric field, drift well W is the width of the depletion region of drift/well junction.
According to the RESURF theory, before the avalanche breakdown at the drift /well junction, the drift region must be fully depleted. So the following equation can be derived.
22
2)(2)(c a d s sub dritf d a E N N W N N q ≤+ε (4) Defining D W N sub drift d =(drift do), sub drift W is the vertical width of the depletion region when the drift region is fully depleted. The critical electric field of Si is about 4×105v/cm.
If a d N N 10=，we can drive that 212108.0−×≤cm D .
furtherly
Becau the c E we u is lower than the average. In order to get the expected device, comparing with the normal fabrication character and the simulation result, we defined 212100.1−×=cm D as a reference. The range of D was given from 212108.0−×cm to 212104.1−×cm , and the relationship between breakdown voltage and impurity concentration has been simulated by MEDICI. Finally we get the proper do 212102.1−×=cm D and the drift region depth um W drift 6=. According to the RESURF theory, when breakdown happens in a LDMOS, the drift region is fully depleted, so we have sub drift dritf W W =. Together with the equation that has been defined before we get the concentration of the drift region 315102−×=cm N d (cm ⋅Ω=3.2ρ).
In the RESURF LDMOS, p-type buried layer has also been introduced. It will decrea the curvature of equipotential lines. This electric field shaping method can ensure a thick epitaxy when given the epitaxy concentration and a high impurity concentration when given the epitaxy thickness. Both will result in a decrea in the on-resistance without any reduction of the breakdown voltage.
2.2.2 Inf lue nc e o n t he b r eak d ow n v o l ta g e by t he le ng th of f ie ld pla te
偶像爸爸>unknown是什么意思The field plate technique has already been extensively applied in high voltage devices. By adding veral peak electric filed to substitute the maximum peak electric field, the peak electric field in the surface will be obviously reduced. Compared with other mechanics that have the same function, this technique has the advantages that doesn’t need to an increa of the chip area and some extra process. In the following emphasis will be given to the fact that how the field plates on the right and left will affect the breakdown voltage.
The metal field plate on the left is formed by the aluminum electrode extension from the source to the drain. The length of the field plate is X, and it is ud to increa the breakdown voltage by reducing the peak electric field in the end of the poly-gate. As shown in Figure 2 (a), the potential lines are more intensive at the end of the poly-gate when no field gate is applied. But when metal fiel
d plate is introduced, the potential lines at the end of the poly-gate are moderated. And the peak electric field transfers from B to C, shown in Figure 2 (b). So the field plate here can play a great part in the reducing of the peak electric in the end of the poly-gate.
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(a) (b)
Figure 2: (a) Potential distribution when X=0um
(b) Potential distribution when X=6um
Similarly, the right side of the field plate can also make a decrea to the curvature of the equipotential lines and thus improve the breakdown voltage. More simulations have down by changing the length of the field plate on both side and finally a typical value that fit the design was obtained, the values are um X 6=,um K 10=.
2.2.3 Influence on the breakdown voltage and on-resistance by the leng th of
d r i f t r eg i on
In order to get a high breakdown voltage, the drift region length should also be extended. But meanwhile, the width of the drift region also has to be extended for the sake of reducing the on- resistance. This is why most of the power devices always have large areas. In order to find the proper drift length, more simulations about the breakdown voltage and on-resistance have been done by MEDICI at different drift region lengths. Figure 3 shows the simulation result.
Figure 3: Profiles of BV and sp on R . at
杭州计算机学校Different d L As shown in Figure3, when d L increas, BV and sp on R . (Defined A R R on sp on ⋅=.
, A is the area of the device) increa at the same time. To get the expected device, we choo d L as 75um or 80um, and the simulation results are as follows,
Table 1: Simulation Result when Do is 1.2×1012cm -2
Ld
(um)
sp on R . (Ω·um 2) Ron （W ＝2630um) (Ω) 75 23.44 118．83 80
26．09 124.00
