JEDEC
STANDARD
Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress JESD28-A
(Revision of JESD28)
DECEMBER 2001
恋人未满英文版JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subquently reviewed and approved by the JEDEC legal counl.
JEDEC standards and publications are designed to rve the public interest through eliminating misunderstandings between manufacturers and purchars, facilitating interchangeability and improvement of products, and assisting the purchar in lecting and obtaining with minimum delay the proper product for u by tho other than JEDEC members, whether the standard is to be ud either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or process. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications.
The information included in JEDEC standards and publications reprents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standard or publication may be further procesd and ultimately become an ANSI/EIA standard.
No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met.
日语能力测试Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addresd to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, (703)907-7559 or
Published by
©JEDEC Solid State Technology Association 2001
2500 Wilson Boulevard
Arlington, VA 22201-3834
This document may be downloaded free of charge; however JEDEC retains the
copyright on this material. By downloading this file the individual agrees not to
charge for or rell the resulting material.
PRICE: Plea refer to the current
Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada 1-800-854-7179, International (303) 397-7956
Printed in the U.S.A.
All rights rerved
JEDEC Standard No. 28-A
A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-
INDUCED DEGRADATION UNDER DC STRESS
CONTENTS
Page Introduction ii
法语考试马丁路德金 我有一个梦想1 Scope 1
playbadminton
benjie2 Applicable standards 1
3 Terms and definitions 2
浦东少儿英语培训4 Technical requirements 4 4.1 Equipment requirements 4 4.2 Test structure requirements 4
4.3 Measurement requirements 4
5 Hot carrier stress test procedure 5 5.1 Determining stress bias conditions
6 5.2 Selecting test devices
7 5.3 Initial characterization 7 5.4 Stress cycle 7 5.5 Interim characterization 7
sine5.6 Stress termination 7
6 Data analysis 8
7 Precautions 9 7.1 Test sample 9 7.2 Stress 9 7.3 Interim measurements 9
全国研究生网上报名7.4 Data analysis 10
美女与野兽动画片8 Required reporting 10 8.1 Test transistor identification 10 8.2 V DD, V BB 10 8.3 MOSFET channel length and width 10 8.4 V DS at stress, V BS at stress, V GS at stress 10 8.5 Initial I B at stress 10 8.6 Initial I D(lin), g m(max), V T(ci), V T(ext), I D(sat) 11 8.7 t TAR for I D(lin), g m(max), V T(ci), V T(ext), I D(sat) 11 8.8 Total test time 11 8.9 Measurement temperature 11
-i-
