t_multicycle_path语法说明【转载】

更新时间:2023-05-18 16:13:43 阅读: 评论:0

t_multicycle_path语法说明【转载】
(转载)
(其实多看⼿册就知道原因了)
Q:多周期路径中的检查保持时间时刻,为什么默认是在建⽴时间检查的前⼀个cycle?请⼤家谈谈⾃⼰的理解。如:Set_multicycle_path -tup 7 -to [whatever] 那么hold time 应该在7-1这个cycle检查,为什么?
A:呼吁英文
多周期路径中检查保持时间,如果你对建⽴时间设置多周期,那么保持时间检查就默认在前⼀建⽴时间,⽐如:
楼主所设定:
reali和realizet_multicycle_path -tup 7 -to [whatever]
若⼀个周期为10ns,则此时数据到达触发器的时间范围应该是:[60+Th,70-Ts]
一对一在线辅导2013年诺贝尔文学奖⽽⾄于为什么,⼀⽅⾯就是primetime等的默认,另外就是在检查单周期时,通常也是要求如此的,即要
求数据在[Th,10-Ts]时间范围内到达。(Th表⽰保持时间,Ts表⽰建⽴时间)
但倘若你同时设定建⽴时间和保持时间都为多周期路径约束,那么延时范围就可以变⼤,如:
t_multicycle_path -tup 7 -to [clk]
t_multicycle_path -hold 6 -to [get_pins C_reg /D]
那么此时的保持时间检查就在Th时,⽽不是在60+Th时,⽽此时的arrival time的范围就变⼤了
是:[Th,70-Ts]
所以⼀般采⽤后者设定,这样多周期路径部分电路的优化范围就变⼤了。
重申⼀点:采⽤
t_multicycle_path -tup 7 -to [clk]
t_multicycle_path -hold 6 -to [get_pins C_reg/D]
这样多周期路径部分电路的优化范围确实变⼤了,但是会有亚稳态的潜在危险,所以要⼩⼼!
jetty>ebra>美甲培训中心
⽽只⽤:
t_multicycle_path -tup 7 -to [clk]
你⼜必须保证path_delay⾜够⼤,不会产⽣hold-time violation,DC⼏乎不可能做到这⼀点。
加register-enabling logic解决亚稳态
指挥官英文⾸先:
⽆论是单周期还是多周期,hold检查都默认为tup的前⼀个时钟。
你写了t_multicycle_path -tup 7 -to [clk]之后,dc何pt默认t_multicycle_path -hold 0 -to [get_pins C_reg/D],如果你不写
t_multicycle_path -hold 6 -to [get_pins C_reg/D]
其他的Harva 说得很详细了。
其次:
如richardhuang1 所说,加使能,在该采的时钟周期采数据。
Harva 和handsome说得很精彩,我帖⼀个synopsys的解释,⼤家共同学习.
t_multicycle_path and hold checks
-----------------------------------
Question:
I have a path that is t as multicycle path for the tup check. For some
reason, PrimeTime ems to be treating it as a multicycle path for hold time
checking as well. I'm using:
t_multicycle_path -tup 7 -to [whatever]
海床Why are the hold time checks multicycle?
Answer:
By default, if you specify 't_multicycle_path -tup X', PrimeTime and
Design Compiler assume the datapath could change during any clock before
clock edge number X. To deal with this situation, PrimeTime and Design
Compiler implicitly add 't_multicycle_path -hold 0 -to [whatever]'. This
caylapositions the hold check one clock cycle before the tup check, effectively
constraining the path delay to be between X-1 and X clock cycles, or in
equation form:
X-1 cycles + T_hold < path delay (min)
path delay (max) < X cycles - T_tup
So by default the tools assume you want the path buffered up so that the minimum change is > X-1 cycles.
This may not be the desired behavior. You can move the hold check back towards the start of the multicycle period by specifying:
t_multicycle_path -hold X-1 -to [whatever]
In the above example, add
t_multicycle_path -hold 6 -to [whatever]
to the constraints and the hold check should occur on the desired edge. Note that moving this check back requires the designer to handle possible metastability. If the endpoint is a multi-bit signal, then you may need
to generate register-enabling logic to avoid clocking data before all of
it is valid.

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