UM10204
I2C-bus specification and ur manual
Rev. 4 — 13 February 2012Ur manual
Document information
Info Content
Keywords I2C, I2C-bus, Standard-mode, Fast-mode, Fast-mode Plus, Fm+,
Ultra Fast-mode, UFm, High Speed, Hs, inter-IC, SDA, SCL, USDA, USCL Abstract Philips Semiconductors (now NXP Semiconductors) developed a simple
bidirectional 2-wire bus for efficient inter-IC control. This bus is called the
Inter-IC or I2C-bus. Only two bus lines are required: a rial data line
(SDA) and a rial clock line (SCL). Serial, 8-bit oriented, bidirectional
data transfers can be made at up to 100kbit/s in the Standard-mode, up to
400kbit/s in the Fast-mode, up to 1Mbit/s in the Fast-mode Plus (Fm+), or
up to 3.4Mbit/s in the High-speed mode. The Ultra Fast-mode is a
uni-directional mode with data transfers of up to 5Mbit/s.
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Revision history Rev Date Description v.420120213Update ur manual.Modifications:•
The format of this document has been redesigned to comply with the new identity guidelines of NXP Semiconductors.•
Legal texts have been adapted to the new company name where appropriate.•
Table “Document information”: added keywords “Ultra Fast-mode”, “UFm”, “USDA” and “USCL”•
New Section 3.1 created and (old) ctions 3.1 to 3.17 are moved under this new ction and renumbered to Section 3.1.1 to Section 3.1.17.•
Section 3.1.12 “Rerved address”, added descriptive line below title of Table 3•
Added (new) Table 4 “Assigned manufacturer IDs”•
Added (new) Section 3.2 “Ultra Fast-mode I 2C-bus protocol”•
Added (new) Section 4.6 “Display Data Channel (DDC)”•
added (new) Section 5.4 “Ultra Fast-mode”
•Table 9 “Characteristics of the SDA and SCL I/O stages”:
–symbol V hys : deleted condition “V DD >2V”; deleted condition “V DD <2V” and its values
–symbol V OL3 replaced with symbol V OL2; added (new) Table note [3]
–parameter description for t of corrected from “output fall time from V IHmax to V ILmax ” to “output
time from V IHmin to V ILmax ”.
–t of Min values for Fast-mode and Fast-mode Plus are changed to “20ns (V DD /5.5V)”
•Table 10 “Characteristics of the SDA and SCL bus lines for Standard, Fast, and Fast-mode Plus
I 2C-bus devices [1]”:2012年12月1日
–t r Min value for Fast-mode changed from “20+0.1C b ns” to “20ns”
–t f Min values for Fast-mode and Fast-mode Plus are changed to “20ns (V DD /5.5V)”
•
Table 11 “Characteristics of the SDAH, SCLH, SDA and SCL I/O stages for Hs-mode I 2C-bus devices”: cond Condition for V OL changed from “V DD <2V” to “V DD ≤2V”•
Added (new) Section 6.3 “Ultra Fast-mode devices”.•
Section 7.1 “Pull-up resistor sizing”, third paragraph changed from “... is a function of the ri time minimum (t r ) ...” to “... is a function of the ri time maximum (t r ) ...”v.320070619Many of today’s applications require longer bus and/or faster speeds. Fast-mode Plus was
introduced to meet this need by increasing drive strength by as much as 10× and increasing the data
rate to 1Mbit/s while maintaining downward compatibility to Fast-mode and Standard-mode speeds
and software commands.
v2.12000Version 2.1 of the I 2C-bus specification
v2.01998The I 2C-bus has become a de facto world standard that is now implemented in over 1000different ICs
and licend to more than 50 companies. Many of today’s applications, however, require higher bus
speeds and lower supply voltages. This updated version of the I 2C-bus specification meets tho
requirements.
v1.01992Version 1.0 of the I 2C-bus specification
Original 1982
first relea
1. Introduction
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The I2C-bus is a de facto world standard that is now implemented in over 1000 different
ICs manufactured by more than 50 companies. Additionally, the versatile I2C-bus is ud
in various control architectures such as System Management Bus (SMBus), Power
Management Bus (PMBus), Intelligent Platform Management Interface (IPMI), Display
Data Channel (DDC) and Advanced Telecom Computing Architecture (ATCA).
This document assists device and system designers to understand how the I2C-bus works
and implement a working application. Various operating modes are described. It contains
armageddona comprehensive introduction to the I2C-bus data transfer, handshaking and bus
arbitration schemes. Detailed ctions cover the timing and electrical specifications for the
I2C-bus in each of its operating modes.
Designers of I2C-compatible chips should u this document as a reference and ensure
that new devices meet all limits specified in this document. Designers of systems that
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include I2C devices should review this document and also refer to individual component
data sheets.
2. I2C-bus features
In consumer electronics, telecommunications and industrial electronics, there are often
many similarities between emingly unrelated designs. For example, nearly every
system includes:
•Some intelligent control, usually a single-chip microcontroller
•General-purpo circuits like LCD and LED drivers, remote I/O ports, RAM,
EEPROM, real-time clocks or A/D and D/A converters
mindyourlanguage•Application-oriented circuits such as digital tuning and signal processing circuits for
radio and video systems, temperature nsors, and smart cards
To exploit the similarities to the benefit of both systems designers and equipment
manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips
Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus旅行的艺术
for efficient inter-IC control. This bus is called the Inter IC or I2C-bus. All I2C-bus
compatible devices incorporate an on-chip interface which allows them to communicate
directly with each other via the I2C-bus. This design concept solves the many interfacing
problems encountered when designing digital control circuits.
Here are some of the features of the I2C-bus:
•Only two bus lines are required; a rial data line (SDA) and a rial clock line (SCL).
•Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as
master-transmitters or as master-receivers.
•It is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer.
•Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100kbit/s in
the Standard-mode, up to 400kbit/s in the Fast-mode, up to 1Mbit/s in Fast-mode
Plus, or up to 3.4Mbit/s in the High-speed mode.
•Serial, 8-bit oriented, unidirectional data transfers up to 5Mbit/s in Ultra Fast-mode
•On-chip filtering rejects spikes on the bus data line to prerve data integrity.
•The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance. More capacitance may be allowed under some
conditions. Refer to Section7.2.
Figure1 shows an example of I2C-bus applications.
2.1 Designer benefits
I2C-bus compatible ICs allow a system design to progress rapidly directly from a
functional block diagram to a prototype. Moreover, since they ‘clip’ directly onto the
I2C-bus without any additional external interfacing, they allow a prototype system to be modified or upgraded simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.
Here are some of the features of I2C-bus compatible ICs that are particularly attractive to designers:
•Functional blocks on the block diagram correspond with the actual ICs; designs proceed rapidly from block diagram to final schematic.december是什么意思
•No need to design bus interfaces becau the I2C-bus interface is already integrated on-chip.
•Integrated addressing and data-transfer protocol allow systems to be completely software-defined.
•The same IC types can often be ud in many different applications.
•Design-time reduces as designers quickly become familiar with the frequently ud functional blocks reprented by I2C-bus compatible ICs.
•ICs can be added to or removed from a system without affecting any other circuits on the bus.
•Fault diagnosis and debugging are simple; malfunctions can be immediately traced.
•Software development time can be reduced by asmbling a library of reusable software modules.
In addition to the advantages, the CMOS ICs in the I2C-bus compatible range offer
designers special features which are particularly attractive for portable equipment and battery-backed systems.
They all have:
•Extremely low current consumption
•High noi immunity
employer•Wide supply voltage range
•Wide operating temperature range.
2.2 Manufacturer benefits
I2C-bus compatible ICs not only assist designers, they also give a wide range of benefits to equipment manufacturers becau:
•The simple 2-wire rial I2C-bus minimizes interconnections so ICs have fewer pins and there are not so many PCB tracks; result — smaller and less expensive PCBs.
•The completely integrated I2C-bus protocol eliminates the need for address decoders and other ‘glue logic’.
•The multi-master capability of the I2C-bus allows rapid testing and alignment of end-ur equipment via external connections to an asmbly line.
•The availability of I2C-bus compatible ICs in various leadless packages reduces space requirements even more.
The are just some of the benefits. In addition, I2C-bus compatible ICs increa system design flexibility by allowing simple construction of equipment variants and easy
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upgrading to keep designs up-to-date. In this way, an entire family of equipment can be developed around a basic model. Upgrades for new equipment, or enhanced-feature
models (that is, extended memory, remote control, etc.) can then be produced simply by clipping the appropriate ICs onto the bus. If a larger ROM is needed, it is simply a matter of lecting a microcontroller with a larger ROM from our comprehensive range. As new ICs superde older ones, it is easy to add new features to equipment or to increa its performance by simply unclipping the outdated IC from the bus and clipping on its
successor.
