U | To |
Scope | Select the scope of the design rules check. The scope can cover the entire design, or lected schematic folders and pages. |
Mode | 3602Specify to check either instances or occurrences.Capture automatically ts this option bad on the project type. All designs default to u instances. If a PCB or Schematic design is complex or has occurrence properties, the default shifts to occurrences. Capture recommends the preferred mode, which you can override. |
Action 英语新闻网 | Specifies either a design rules check, deletion of existing DRC markers or creating DRC markers for warning. Note: The DRC markers are automatically deleted when you run a subquent design rules check. U the Ignore DRC Warnings option to specify any DRC Warnings that you do not want to be checked during the DRC check and netlisting. For example, to ignore the ALG0051 or ALG0016 warnings during netlist, specify the in the Ignore Warnings dialog. |
Design Rules | Select the type of rules to run, electrical and / orphysical. |
Report file | Specify the path and file name for the report. |
View Output | Open the design rules check report file in a text editor. |
Brow | Displays a standard Windows dialog box for lecting files. |
Electrical Rules | |
U | To |
Check single node nets | Check if the design contains any nets with only one connection. |
Check no driving source and Pin type conflicts | |
Check duplicate net names | Check if the design contains any duplicate net names. |
Check off-page connectorconnections | Verify that off-page connector nets on a schematic page match tho on other schematic pages. |
Check hierarchical portconnections | Verify that hierarchical pins in a hierarchical block match hierarchical ports in the child schematic folder or folders. Errors are generated if the number of hierarchical ports and hierarchical pins differ between the parent and child schematic folders. Also generates errors if the types of hierarchical ports are not identical between the parent and child schematic folders. |
Check unconnected bus nets 笔试英文 | Check for and reports all unconnected bus nets. This check will run for all unconnected bus nets across schematics in a design. |
Check unconnected pins | Check for any pins on the design that are unconnected or do not have no-connect attached. |
Check SDT compatibility | Check for SDT compatibility. For more information about SDT compatibility, eSaving in SDT format. |
Reports | |
U 凸台 | To |
Report all net names | List the names of all nets in the report file. |
Report off-grid objects | List all objects that are on Fine grid in the report file. |
Report hierarchical ports and off-page connectors | List all hierarchical ports and off-page connectors in the report file. | 生活需要挫折
行走在消逝中Report misleading tapconnections | Checks for and reports tho signals that are wrongly connected through a Bus Tap to a bus. Also checks for missing bus taps. |
Physical Rules | |
U | To |
Check power pin visibility | Check if the visibility property of a power pin on one ction of multi-ction part is different from the corresponding power pin on another ction of the part. |
Check missing/illegal PCB Footprint property | Check if the PCB footprint property on a part is missing or the property defined is illegal. |
Check Normal Convert view sync | Check if the pin numbers on the normal view of a part are different from the pin numbers on the convert view. |
Check incorrect Pin_Groupassignment | hub是什么Check if all pins in same pin group in a part are of the same type. |
Check high speed props syntax | Check the syntax of the high speed properties of the nets in the design. |
Check missing pin numbers | Check if any part on the design has missing pin numbers. |
Check device with zero pins | Check if any part on the design has no pin on the part. |
Check power ground short | Check if the type of power pin name inside a part is connected to a net on the schematic with a different name. |
Check Name Prop consistency | Check if the occurrences of a hierarchical block have the same "Name" property. |
Reports | |
U | To |
Report Visible unconnected power pins | List the names of all visible unconnected power pins. |
Report unud part packages | List the names of any unud part packages. |
Report invalid packaging | List any invalid packaging. |
Report identical part references | List any identical part references. |
U | To |
Matrix | canxueSet the rules ud by the Design Rules Check when testing connections between pins, hierarchical blocks, and hierarchical ports. The pins, hierarchical ports, and off-page connectors are listed in columns and rows in the table. A test is reprented by the interction of a row and column. Either the interction of a row and column is empty, or it contains a "W" or an "E." An empty interction reprents a valid connection, a "W" is a warning, and an "E" reprents an error. You can cycle through the three ttings by pointing to an interction and clicking the mou button until the desired tting displays. You can also type W for warning, E for error, and N for an empty interction. In addition to the keys, you can u the arrow keys to lect other interctions. |
Restore defaults | Restore the ERC matrix to its default values. |
本文发布于:2023-05-18 10:37:06，感谢您对本站的认可！
本文链接：https://www.wtabcd.cn/fanwen/fan/90/113154.html
版权声明：本站内容均来自互联网，仅供演示用，请勿用于商业和其他非法用途。如果侵犯了您的权益请与我们联系，我们将在24小时内删除。
| 留言与评论（共有 0 条评论） |
