REV.C
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a
Integrated Circuit
Voltage-to-Frequency Converter
AD537*
PRODUCT DESCRIPTION
The AD537 is a monolithic V-F converter consisting of an input amplifier, a precision oscillator system, an accurate internal ref-erence generator and a high current output stage. Only a single external RC network is required to t up any full-scale (F.S.)frequency up to 100kHz and any F.S. input voltage up to
±30V. Linearity error is as low as ±0.05% for 10kHz F.S., and operation is guaranteed over an 80dB dynamic range. The over-all temperature coefficient (excluding the effects of external components) is typically ±30ppm/°C. The AD537 operates from a single supply of 5V to 36V and consumes only 1.2mA quiescent current.
A temperature-proportional output, scaled to 1.00mV/K,enables the circuit to be ud as a reliable temperature-to-frequency converter; in combination with the fixed reference output of 1.00V, offt scales such as 0°C or 0°F can be generated.The low drift (1µV/°C typ) input amplifier allows operation directly from small signals (e.g., thermocouples or strain gages)while offering a high (250M Ω) input resistance. Unlike most V–F converters, the AD537 provides a square-wave output, and can drive up to 12 TTL loads, LEDs, very long cables, etc.The excellent temperature characteristics and long-term stability of the AD537 are guaranteed by the primary bandgap reference generator and the low T.C. silicon chromium thin film resistors ud throughout.
The device is available in either a 14-lead ceramic DIP or a 10-lead metal can; both are hermetically aled packages.
*Protected by Patent Nos. 3,887,963 and RE 30,586.
FEATURES
Low Cost A–D Conversion Versatile Input Amplifier
Positive or Negative Voltage Modes Negative Current Mode
High Input Impedance, Low Drift Single Supply, 5V to 36V Linearity: ؎0.05% FS
Low Power: 1.2mA Quiescent Current Full-Scale Frequency up to 100kHz 1.00V Reference
Thermometer Output (1mV/K) F-V Applications
MIL-STD-883 Compliant Versions Available
PIN CONFIGURATIONS
D-14 Package H-10A Package
LOGIC GND
SYNC
+V IN V TEMP V REF
liarI IN –V IN
S OS OS S
+V S
S
(CONNECTED TO CASE)
V The AD537 is available in three performance/temperature grades; the J and K grades are specified for operation over the 0°C to +70°C range while the AD537S is specified for operation over the extended temperature range, –55°C to +125°C.
PRODUCT HIGHLIGHTS
1. The AD537 is a complete V-F converter requiring only an external RC timing network to t the desired full-scale fre-quency and a lectable pull-up resistor for the open collec-tor output stage. Any full-scale input voltage range from 100mV to 10 volts (or greater, depending on +V S ) can be accommodated by proper lection of timing resistor. The full-scale frequency is then t by the timing capacitor from the simple relationship, f = V/10RC.
新概念学习2.The power supply requirements are minimal, only 1.2mA quiescent current is drawn from a single positive supply from 4.5volts to 36 volts. In this mode, positive inputs can vary from 0 volts (ground) to (+V S – 4) volts. Negative inputs can easily be connected for below ground operation.
3.F-V converters with excellent characteristic are also easy to build by connecting the AD537 in a pha-locked loop. Ap-plication particulars are shown in Figure 6.grossman
4.The versatile open-collector NPN output stage can sink up to 20mA with a saturation voltage less than 0.4 volts. The Logic Common terminal can be connected to any level be-tween ground (or –V S ) and 4 volts below +V S . This allows easy direct interface to any logic family with either positive or negative logic levels.
5.The AD537 is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Product Databook or current AD537/883B data sheet for detailed specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: Fax: 781/326-8703© Analog Devices, Inc., 2000
AD537–SPECIFICATIONS(typical @ +25؇C with V S (total) = 5 V to 36 V, unless otherwi noted)
AD537KD AD537SD1 Model AD537JH AD537JD AD537KH AD537SH1 CURRENT-TO-FREQUENCY CONVERTER
Frequency Range0kHz to 150kHz***
Nonlinearity1
f MAX = 10kHz0.15% max (0.1% typ)*0.07% max**
f MAX = 100kHz0.25% max (0.15% typ)*0.1% max**
Full-Scale Calibration Error
C = 0.01µF, I IN = 1.000mA±10% max±7% max±5% max* *
vs. Supply (f MAX < 100kHz)±0.1%/V max (0.01% typ)***
vs. Temp (T MIN to T MAX)±150ppm/°C max (50ppm typ)*50ppm/°C max (30ppm typ)2250ppm/°C max ANALOG INPUT AMPLIFIER
(Voltage-to-Current Converter)
Voltage Input Range
Single Supply0 to (+V S – 4) Volts (min)***
Dual Supply–V S to (+V S – 4) Volts (min)*** Input Bias Current
(Either Input)100nA*** Input Resistance (Noninverting)250MΩ***
Input Offt Voltage
(Trimmable in “D” Package Only)5mV max* 2 mV max**
vs. Supply200µV/V max100µV/V max100µV/V max**
vs. Temp (T MIN to T MAX)5µV/°C*1µV/°C10µV/°C max Safe Input Voltage3±V S*** REFERENCE OUTPUTS
Voltage Reference
Absolute Value 1.00 Volt ± 5% max***
vs. Temp (T MIN to T MAX)50ppm/°C*100 ppm/°C max**
vs. Supply±0.03%/V max***
Output Resistance4380Ω*** Absolute Temperature Reference5
Nominal Output Level 1.00mV/K***
Initial Calibration @ +25°C298mV (±5mV typ)*298mV (±5mV max)**
Slope Error from 1.00mV/K±0.02mV/K***
Slope Nonlinearity±0.1K***
Output Resistance5900Ω***
OUTPUT INTERFACE (Open Collector Output)
(Symmetrical Square Wave)
Output Sink Current in Logic “0”
V OUT = 0.4V max (T MIN to T MAX)20mA min20mA min20mA min10 mA min Output Leakage Current in Logic “1”
(T MIN to T MAX)200nA max**2µA max Logic Common Level Range –V S to (+V S – 4) Volts***
Ri/Fall Times (C T = 0.01µF)
I IN = l mA0.2 µs***
I IN = 1µA1µs***
POWER SUPPLY
Voltage, Rated Performance
Single Supply 4.5V to 36V***
Dual Supply±5V to ±18V*** Quiescent Current 1.2 mA (2.5 mA max)*** TEMPERATURE RANGE
Rated Performance0°C to +70°C**–55°C to +125°C Storage–65°C to +150°C***
PACKAGE OPTIONS6, 7
D-14 Ceramic DIP AD537JD AD537KD AD537SD H-10A Header AD537JH AD537KH AD537SH NOTES
*Specifications same as AD537JH.
**Specifications same as AD537K.
1Nonlinearity is specified for a current input level (I
IN ) to the converter from 0.1µA to 1000µA. Converter has 100% overrange capability up to I IN = 2000µA with slightly
reduced linearity. Nonlinearity is defined as deviation from a straight line from zero to full scale, expresd as a percentage of full scale.
2Guaranteed not tested.
3Maximum voltage input level is equal to the supply on either input terminal. However, large negative voltage levels can be applied to the negative terminal if the input is scaled to a nominal 1mA full scale through an appropriate value resistor (See Figure 2).
4Loading the 1.0 volt or 1mV/K outputs can cau a significant change in overall circuit performance, as indicated in the applications ction. To maintain normal operation, the outputs should be operated into the external buffer or an external amplifier.
5Temperature reference output performance is specified from 0°C to +70°C for “J” and “K” devices, –55°C to +125°C for “S” model.
6D = Ceramic DIP; H = Hermetic Metal Can. For outline information e Package Information ctio
n.
7For AD537/883B specifications, refer to Analog Devices Military Products Databook.
Specifications subject to change without notice.
REV. C
–2–
Applying the AD537
CIRCUIT OPERATION
Block diagrams of the AD537 are shown above. A versatile operational amplifier (BUF) rves as the input stage; its pur-po is to convert and scale the input voltage signal to a drive current in the NPN follower. Optimum performance is achieved when, at the full-scale input voltage, a 1mA drive current is delivered to the current-to-frequency converter. The drive cur-rent to the current-to-frequency converter (an astable multivibrator) provides both the bias levels and the charging current to the externally connected timing capacitor. This “adaptive” bias scheme allows the oscillator to provide low non-linearity over the entire current input range of 0.1µA to
2000µA. The square wave oscillator output goes to the output driver which provides a floating ba drive to the NPN power transistor. This floating drive allows the logic interface to be ref-erenced to a different level than –V S. The “SYNC” input (“D”package only) allows the oscillator to be slaved to an external master oscillator; this input can also be ud to shut off the oscillator.
The reference generator us a bandgap circuit (this allows single-supply operation to 4.5 volts which is not possible with low T.C. Zeners) to provide the reference and bias levels for the amplifier and oscillator stages. The reference generator also pro-vides the precision, low T.C. 1.00 volt output and the V TEMP output which tracks absolute temperature at 1mV/K.
V-F CONNECTION FOR POSITIVE INPUT VOLTAGES The positive voltage input range is from –V S (ground in single supply operation) to 4 volts below the positive supply. The con-nection shown in Figure 1 provides a very high (250MΩ) input impedance. The input voltage is converted to the proper drive current at Pin 3 by lecting a scaling resistor. The full-scale current is 1mA, so, for example a 10 volt range would require a nominal 10kΩ resistor. The trim range required will depend on capacitor tolerance. Full-scale currents other than 1mA can be chon, but linearity will be reduced; 2mA is the maximum allowable drive.
As indicated by the scaling relationship in Figure 1, a 0.01µF timing capacitor will give a 10kHz full-scale frequency, and
0.001µF will give 100kHz with a 1mA drive current. The maximum frequency is 150kHz. Polystyrene or NPO ceramic capacitors are preferred for T.C. and dielectric absorption; polycarbonate or mica are acceptable; other types will degrade linearity. The capacitor should be wired very clo to the
AD537.
Figure 1.Standard V-F Connection for Positive Input
Voltages V-F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE OR CURRENT
A wide range of negative input voltages can be accommodated with proper lection of the scaling resistor, as indicated in Fig-ure 2. This connection, unlike the buffered positive connection, is not high impedance since the 1mA F.S. drive current must be supplied by the signal source. However, very large negative volt-ages beyond the supply can be handled easily; just modify the scaling resistors appropriately. Diode CR1 (HP50822811) is necessary for overload and latchup protection for current or voltage inputs.
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If the input signal is a true current source, R1 and R2 are not ud. Full-scale calibration can be accomplished by connecting a 200kΩ pot in ries with a fixed 27kΩ from Pin 7 to –V S (e calibration ction, below).
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Figure 2.V-F Connections for Negative Input Voltage or Current
CALIBRATION
现在进行时的构成There are two independent adjustments: scale and offt. The first is trimmed by adjustment of the scaling resistor R and the cond by the (optional) potentiometer connected to +V S and the V OS pins (“D” package only). Preci calibration requires the u of an accurate voltage standard t to the desired FS value and a frequency meter; a scope is uful for monitoring output waveshape. Verification of linearity requires the availability of a switchable voltage source (or a DAC) having a linearity error below ±0.005%, and the u of long measurement intervals to minimize count uncertainties. Every AD537 is automatically tested for linearity, and it will not usually be necessary to perform this verification, which is both tedious and time-consuming. Although drifts are small it is good practice to allow the operat-ing environment to attain stable temperature and to ensure that the supply, source and load conditions are proper. Begin by t-ting the input voltage to 1/10,000 of full scale. Adjust the offt pot until the output frequency is 1/10,000 of full scale (for ex-ample 1Hz for F
S of 10kHz). This is most easily accomplished using a frequency meter connected to the output. Then apply the FS input voltage and adjust the gain pot until the desired FS frequency is indicated. In applications where the FS input is small, this adjustment will very slightly affect the offt voltage, due to the input bias current of the buffer amplifier. A change of l kΩ in R will affect the input by approximately 100µV, which is as much as 0.1% of a 100mV FS range. Therefore, it may be necessary to repeat the offt and scale adjustments for the high-est accuracy. The design of the input amplifier is such that the input voltage drift after offt nulling is typically below lµV/°C.
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AD537
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–4–The –V IN , +V IN and I IN pins should not be driven more than
300mV below –V S . This would cau internal junctions to con-duct, possibly damaging the IC. The AD537 can be protected from “below –V S ” inputs by a Schottky diode, CR1 (HP5082-2811) as shown in Figure 3. It is also desirable not to drive +V IN , –V IN and I IN above +V S . In operation, the converter will become very nonlinear for inputs above (+V S – 3.5V). Control currents above 2mA will also cau nonlinearity.
The 80 dB dynamic range of the AD537 guarantees operation from a control current of 1mA (nominal FS) down to 100nA (equivalent to 1mV to 10V FS). Below 100nA improper op-eration of the oscillator may result, causing a fal indication of input amplitude. In many cas this might be due to short-lived noi spikes which become added to the input. For example,when scaled to accept a FS input of 1 V, the –80dB level is only 100µV, so when the mean input is only 60dB below FS (1mV), noi spikes of 0.9mV are sufficient to cau momen-tary malfunction.
This effect can be minimized by using a simple low-pass filter ahead of the converter and a guard ring around the I IN or –V IN pins. For a FS of 10kHz a single-pole filter with a time-constant of 100
ms (Figure 2) will be suitable, but the optimum configu-ration will depend on the application and type of signal process-ing. Noi spikes are only likely to be a cau of error when the input current remains near its minimum value for long periods of time; above 100nA (1mV) full integration of additive input noi occurs.
The AD537 is somewhat susceptible to interference from other signals. The most nsitive nodes (besides the inputs) are the capacitor terminals and the SYNC pin. The timing capacitor should be located as clo as possible to the AD537 to minimize signal pickup in the leads. In some cas, guard rings or shield-ing may be required. The SYNC pin should be decoupled through a 0.005µF (or larger) capacitor to Pin 13 (+V S ). This minimizes the possibility that the AD537 will attempt to syn-chronize to a spurious signal. This precaution is unnecessary on the metal can package since the SYNC function is not brought out to a package pin and is thus not susceptible to pickup.
DECOUPLING
It is good engineering practice to u bypass capacitors on the supply-voltage pins and to inrt small-valued resistors (10Ω to 100Ω) in the supply lines to provide a measure of decoupling between the various circuits in a system. Ceramic capacitors of 0.1µF to 1.0µF should be applied between the supply-voltage pins and analog signal ground for proper bypassing on the AD537.
A decoupling capacitor may also be uful from +V S to SYNC in tho applications where very low cycle-to-cycle period varia-tion (jitter) is demanded. By placing a capacitor across +V S and SYNC this noi is reduced. On the 10kHz FS range, a 6.8µF capacitor reduces the jitter to one in 20,000 which adequate for most applications. A tantalum capacitor should be ud to avoid errors due to dc leakage.
In some cas the signal may be in the form of a negative cur-rent source. This can be handled in a similar way to a negative input voltage. However, the scaling resistor is no longer re-quired, eliminating the capability of trimming full scale in this fashion. Since it will usually be impractical to vary the capaci-tance, an alternative calibration scheme is needed. This is shown in Figure 3. A resistor-potentiometer connected from the V R output to –V S will alter the internal operating conditions in a predictable way, providing the necessary adjustment range.With the values shown, a range of ±4% is available; a larger range can be attained by reducing R1. This technique does not degrade the temperature-coefficient of the converter, and the linearity will be as for negative input voltages. The minimum supply voltage may be ud.
Unless it is required to t the input node at exactly ground potential, no offt adjustment is needed. The capacitor C is -lected to be 5% below the nominal value; with R2 in its midposition the output f
requency is given by:
f =
I
10.5×C where f is in kHz, I is in mA and C is in µF. For example, for a FS frequency of 10kHz at a FS input of 1mA, C = 9500pF.Calibration is effected by applying the full-scale input and ad-justing R2 for the correct reading.
This alternative adjustment scheme may also be ud when it is desired to prent an exact input resistance in the negative volt-age mode. The scaling relationship is then
f =
V
R EXACT ×110.5C
The calibration procedure is then similar to that ud for posi-tive input voltages, except that the scale adjustment is by means of R2.
V Figure 3.Scale Adjustment for Current Inputs INPUT PROTECTION
The AD537 was designed to be ud with a minimum of addi-tional hardware. However, the successful application of a preci-sion IC involves a good understanding of possible pitfalls and the u of suitable precautions.
AD537
blandREV. C –5–
NONLINEARITY SPECIFICATION
The preferred method for specifying linearity error is in terms of the maximum deviation from the ideal relationship after cali-brating the converter at full scale and “zero ”. This error will vary with the full-scale frequency and the mode of operation.The AD537 operates best at a 10kHz full-scale frequency with a negative voltage input; the linearity is typically within ±0.05%.Operating at higher frequencies or with positive inputs will degrade the linearity as indicates in the Specification table. The shape of a typical linearity plot is given in Figure 4.
0.180.040.100.06100.081
0.16
0.120.1410k
搭档的英语1k 100
OUTPUT FREQUENCY – Hz
N O N L I N E A R I T Y – % O F F U L L S C A L
E
be forever–0.08
–0.02–0.06–0.0400.02
Figure 4a. Typical Nonlinearity Error Envelopes with 10kHz F.S. Output
0.180.040.100.061000.0810
0.16
0.120.14100k
10k 1k OUTPUT FREQUENCY – Hz
N O N L I N E A R I T Y – % O F F U L L S C A L E
–0.08
–0.02–0.06–0.0400.02
Figure 4b. Typical Nonlinearity Error with 100kHz F.S.
Output
OUTPUT INTERFACING CONSIDERATIONS
The design of the output stage allows easy interfacing to all digi-tal logic families. The collector and emitter of the output NPN transistor are both uncommitted; the emitter can be tied to any voltage between –V S and 4 volts below +V S . The open collector can be pulled up to a voltage 36 volts above the emitter regard-less of +V S . The high power output stage can supply up to
20mA (10mA for “H ” package) at a maximum saturation volt-age of 0.4 volts. The stage limits the output current at 25mA; it can handle this limit indefinitely without damaging the device.
Figure 5 shows the AD537 with a standard 0 to +10 volt input connection and the output stage connections. The values for the logic common voltage, pull-up resistor, positive logic level, and –V S supply are given in the accompanying chart for veral logic forms.
V Figure 5.Interfacing Standard Logic Families
APPLICATIONS
The diagrams and descriptions of the following applications are provided to stimulate the discerning engineer with alternative circuit design ideas. “Applications of the AD537 IC Voltage-to-Frequency Converter ”, available from Analog Devices on request, covers a wider range of topics and concepts in data conversion and data transmission using voltage-to-frequency converters.
TRUE TWO-WIRE DATA TRANSMISSION
Figure 6 shows the AD537 in a true two-wire data transmission scheme. The twisted-pair transmission lines rves the dual pur-po of supplying power to the device and also carrying fre-q
uency data in the form of current modulation. The PNP circuit at the receiving end reprents a fairly simple way for converting the current modulation back into a voltage square wave which will drive digital logic directly. The 0.6 volt square wave which will appear on the supply line at the device terminals does not affect the performance of the AD537 becau of its excellent supply rejection. Also, note that the circuit operates at nearly constant average power regardless of frequency.
+151k 3.3k
S
Figure 6.True Two-Wire Operation
AD537
REV. C
–6–F-V CONVERTERS
The AD537 can be ud as a high linearity VCO in a pha-locked loop to accomplish frequency-to-
voltage conversion. By operating the loop without a low-pass filter in the feedback path (first-order system), it can lock to any frequency from zero to an upper limit determined by the design, responding in three or four cycles to a step change of input frequency. In practice, the overall respon time is determined by the characteristics of the averaging filter which follows the PLL.
Figure 7 shows a connection using a low power TTL quad
open-collector nand gate which rves as the pha comparator.The input signal should be a pul train or square wave with characteristics similar to TTL or 5-volt CMOS outputs. Any duty cycle is acceptable, but the minimum pul width is 40µs.The output voltage is one volt for a 10kHz input frequency.The output as shown here is at a fairly high impedance level; for many situations an additional buffer may be required.Trimming is similar to V-F application trimming. First t the V OS trimmer to mid-scale. Apply a 10kHz input frequency and trim the 2k Ω potentiometer for 1.00 volts out. Then apply a 10Hz waveform and trim the V OS for 1mV out. Finally, retrim the full-scale output at 10kHz. Other frequency scales can be obtained by appropriate scaling of timing components.
Figure 7. 10kHz F-V Converter
TEMPERATURE-TO-FREQUENCY CONVERSION
The linear temperature-proportional output of the AD537 can be ud as shown in the applications to perform various direct temperature-to-frequency conversion functions; it can also be ud with other external connections in a temperature nsing or compensation scheme. If the nsor output is ud externally,it should be buffered through an op amp since loading that point will cau significant error in the nsor output as well as in the main V-F converter circuitry.
An absolute temperature (Kelvin)-to-frequency converter is very easily accomplished, as shown in Figure 8. The 1mV per K out-put rves as the input to the buffer amplifier, which then scales the oscillator drive current to a nominal 298µA at +25°C
(298K). U of a 1000pF capacitor results in a corresponding frequency of 2.98kHz. Setting the single 2 k Ω trimmer for the correct frequency at a well-defined temperature near +25°C will
normally result in an accuracy of ±2°C from –55°C to +125°C (using an AD537S). An NPO ceramic capacitor is recom-mended to minimize nonlinearity due to capacitance drift.
–V S
(CONNECTED TO CASE)
Figure 8.Absolute Temperature to Frequency Converter OFFSET TEMPERATURE SCALES
Many other temperature scales can be t up by offtting the temperature output with the voltage reference output. Such a scheme is shown by the Celsius-to-frequency converter in
Figure 9. Corresponding component values for a Fahrenheit-to-frequency converter which give 10Hz/°F are given in parenthes.
OUT °C °F)2.74k 500Figure 9.Offt Temperature Scale Converters Centigrade and (Fahrenheit) to Frequency
A simple calibration procedure which will provide ±2°C accu-racy requires substitution of a 7.27k resistor for the ries com-bination of the 6.04k with the 2k trimmer; then simply t the 500Ω trimmer to give 250Hz at +25°C.
High accuracy calibration procedure:1.Measure room temperature in K.
2.Measure temperature output at Pin 6 at that temperature.
3.Calculate offt adjustment as follows:
Offt Voltage (mV ) =
V TEMP (Pin 6) (mV )
Room temp (K )×273.24.Temporarily disconnect 49Ω resistor (or 500Ω pot) and trim 2k Ω pot to give the offt voltage at the indicated node.Reconnect 49Ω resistor.
5.Adjust slope trimmer to give proper frequency at room tem-perature (+25°C = 250Hz).
Adjustment for °F or any other scale is analogous.
