ICL7135 4 1/2 Digit, BCD Output, A/D Converter
The Intersil ICL7135 precision A/D converter, with its multiplexed BCD output and digit drivers, combines dual-slope conversion reliability with +1 in 20,000 count accuracy and is ideally suited for the visual display DVM/DPM market. The 2.0000V full scale capability, auto-zero绯闻女孩第二季, and auto-polarity are cdenmark怎么读ombined with true ratiometric operation, almost ideal differential linearity and true difsmash hitferential input. All necessary active devices are contained on a single CMOS lC, with the exception of display drivers, reference, and a clock.
The ICL7135 brings together an unprecedented combination of high accuracy, versatility, and true economy. It features auto-zero to less than 10µ V, zero drift of less than 1µV/state of play℃, input bias current of 10pA (Max), and rollover error of less than one count. The versatility of multiplexed BCD outputs is incread by the addition of veral pins which allow it to operate in more sophisticated systems. The include STROBE , OVERRANGE , UNDERRANGE , RUN/HOLD and BUSY lines, making it possible to interface the circuit to a microprocessor or UART.
Features
* Accuracy Guaranteed to+1 Count Over Entire 20000 Counts (2.0000V Full Scale)
* Guaranteed Zero Reading for 0V Input
* 1pA Typical Input Leakage Current
* True Differential Input
* True Polarity at Zero Count for Preci Null Detection
* Single Reference Voltage Required
* Over range and Under range Signals Available for Auto-Range Capability
* All Outputs TTL Compatible
* Blinking Outputs Gives Visual Indication of Over range
* Six Auxiliary Inputs/Outputs are Available for Interfacing to UARTs , Microprocessors, or Other Circuitry
* Multiplexed BCD Outputs
* Pb-Free Available (RoHS Compliant)
Detailed Description
Analog Section
Each measurement cycle is divided into four phas. They are (1) auto-zero (AZ), (2) signal-integrate (INT), (3) de-integrate (DE) and (4) zero-integrator (Zl).
Auto-Zero Pha
During auto-zero, three things happen. First, inpu脸盆t high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is clod around the system to c
harge the auto-zero capacitor CAZ to compensate for offt voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the AZ accuracy is limited only by the noise of the system. In any case, the offt referred to the input is less than 10µV.
Signal Integrate Pha
During signal integrate , the auto-zero loop is opened, the internal short is removed, and the intant manernal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range; within one volt of either supply. If, on出国留学保证金 the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to ana英语在线翻译有道log COMMON to establish the correct common-mode voltage. At the end of this phase, the polarity of the integrated signal is latched into the polarity F/F.
De-Integrate Pha
The third pha is de-integrate or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry wbothandithin the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the out- put to return to zero is proportional to the input signal. Specifically the digital reading displayed ttimeis:
Zero Integrator Pha
The final pha is zero integrator. First, input low is shorted to analog COMMON. Second, a feedback loop is clod around the system to input high to cau the integrator output to return to zero. Under normal condition, this pha lasts from 100 to 200 clock puls, but after an over range conversion, it is extended to 6200 clock puls.
Differential Input
The input can accept differential voltages anywhere within the common mode range of the input amplifier; or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range the system has a CMRR of 86dB typical. However, since the integrator also swings with the common mode voltage, care must be exercid to assure the integrator output does not saturate. A worst ca condition would be a large positive common-mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been ud up by the positive common mode voltage. For the critical applications the integrator swing can be reduced to less than the recommended 4V full scale swing with some loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity.
