Features
•Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (L V)•Fast Read Access Time - 120 ns •Internal Program Control and Timer •16K bytes Boot Block With Lockout
•Fast Chip Era Cycle Time - 10 conds
•Byte-by-Byte Programming - 30 µs/Byte Typical •Hardware Data Protection
•DATA Polling For End Of Program Detection •
Low Power Dissipation –25 mA Active Current
–50 µA CMOS Standby Current •Typical 10,000 Write Cycles •Small Packaging
–8 x 8 mm CBGA –8 x 14 mm V-TSOP
Description
The AT49BV/LV040 are 3-volt-only, 4-megabit Flash memories organized as 524,288words of 8-bits each. Manufactured with Atmel’s advanced nonvolatile CMOS tech-nology, the devices offer access times to 120 ns with power dissipation of just 90 mW over the commercial temperature range. When the device is delected, the CMOS standby current is less than 50 µA.
The device contains a ur-enabled “boot block” protection feature. Two versions of the feature are available: the AT49BV/LV040 locates the boot block at lowest order address (“bottom boot”); the AT49BV/LV040T locates it at highest order address (“top boot”).
Pin Configurations
Pin Name Function A0 - A18Address CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7
Data Inputs/Outputs
CBGA T op View
PLCC T
op View
V - TSOP T op View (8 x 14 mm) or T - TSOP T
op View (8 x 20 mm)
(continued)
Block Diagram
Device Operation
READ: The AT49BV/LV040 is accesd like an EPROM. at the memory location determined by the address pins is asrted on the outputs. The outputs are put in the high line control gives designers flexibility in preventing bus con-tention.
ERASURE: Before a byte can be reprogrammed, the 512K bytes memory array (or 496K bytes if the boot block featured is ud) must be erad. The erad state of the memory bits is a logical “1”. The entire device can be erad at one time by using a 6-byte software code. The software chip era code consists of 6-byte load com-mands to specific address locations with a specific data pattern (plea refer to the Chip Era Cycle Waveforms). After the software chip era has been initiated, the device will internally time the era operation so that no external clocks are required. The maximum time needed to era the whole chip is t EC. If the boot block lockout feature has been enabled, the data in the boot ctor will not be erad.
BYTE PROGRAMMING:Once the memory array is erad, the device is programmed (to a logical “0”) on a byte-by-byte basis. Plea note that a data “0” cannot be pro-grammed back to a “1”; only era operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (plea refer to the Command Definitions table). The device will automatically generate the required internal pro-gram puls.
The program cycle has address latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified t BP indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain cure code that is ud to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be acti-vated; the boot block's usage as a write protected region is optional to the us er. The addres s r ange of the AT49BV/LV040 boot block is 00000H to 03FFFH while the address range of the AT49BV/LV040T boot block is 7C000H to 7FFFFH.
To allow for simple in-system reprogrammability, the AT49BV/LV040 does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV/LV040 is performed by eras-ing the entire 4 megabits of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can be end of a byte program cycle has been detected, a new access for a read or program can begin. The typical num-ber of program and era cycles is in excess of 10,000 cycles.
The optional 16K bytes boot block ction includes a repro-gramming write lock out feature to provide data integrity. The boot ctor is designed to contain ur cure code, and when the feature is enabled, the boot ctor is perma-nently protected from being reprogrammed.
AT49BV/LV040
Once the feature is enabled, the data in the boot block can no longer be erad or programmed. Data in the main memory block can still be changed through the regular pro-gramming method. To activate the lockout feature, a ries of six program commands to specific address with spe-cific data must be performed. Plea refer to the Com-mand Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block ction is locked out. When the device is in the soft-ware product identification mode (e Software Product Identification Entry and Exit ctions) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lock-out feature has been activated and the block cannot be programmed. The software product identification code should be ud to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel.
It may be accesd by hardware or software operation. The hardware operation mode can be ud by an external programmer to identify the correct programming algorithm for the Atmel product.
For details, e Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49BV/LV040 features DATA poll-ing to indicate the end of a program cycle. During a pro-gram cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.
TO G G L E B I T:I n a dd i t io n t o D A T A p o l li n g th e AT49BV/LV040 provides another method for determining the end of a program or era cycle. During a program or era operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop tog-gling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49BV/LV040 in the following ways: (a) V CC n: if V CC is below 1.8V (typical), the program function is inhibited. (b) Program inhibits program cycles. (c) Noi filter: puls of less than gram cycle.
INPUT LEVELS:While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adverly affecting the operation of the device. The I/O line s c an on ly be dr iv en fr om 0 to V CC + 0.6V.
元器件交易网
Absolute Maximum Ratings*
T emperature -55°C to +125°C *NOTICE:
Stress beyond tho listed under “Absolute Maxi-mum Ratings” may cau permanent damage to the device. This is a stress rating only and functional operation of the device at the or any other condi-tions beyond tho indicated in the operational c-tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Storage .-65°C to +150°C All Input Voltages (including NC Pins)
四翅滨藜
with Respect -0.6V to +6.25V All Output Voltages
with Respect -0.6V to V CC + 0.6V Voltage on OE
with Respect -0.6V to + 13.5V
Command Definition (in Hex)
Notes:
1.The 16K byte boot ctor has the address range 00000H to 03FFFH for the A T49BV/L V040 and 7C000H to 7FFFFH for the A T49BV/L V040T .
2.
Either one of the Product ID exit commands can be ud.
Command Sequence Bus Cycles 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr
Data
Addr
Data
Addr
Data
Addr
收音机频率
Data
Addr
Data
Read 1Addr D OUT Chip Era 65555AA 2AAA 555555805555AA 2AAA
55
一站到底主持人5555
10
Byte Program 45555AA 2AAA 555555A0Addr D IN Boot Block Lockout (1)65555AA 2AAA 555555805555
AA
2AAA
55
5555
40
Product ID Entry 35555AA 2AAA 55555590Product ID Exit (2)35555AA 2AAA
55
5555
F0
土耳其地毯
Product ID Exit (2)1
XXXX
F0
元器件交易网
AT49BV/LV040
Operating Modes
Notes:
1.X can be V IL or V IH .
2.Refer to AC Programming Waveforms.
3.V H = 12.0V ± 0.5V .
4.Manufacturer Code: 1FH
Device Code: 13H (A T49BV/L V040), 12H (A T49BV/L V040T).5.
See details under Software Product Identification Entry/Exit.
Mode CE OE WE Ai I/O Read V IL V IL V IH Ai D OUT Program (2)
V IL V IH V IL Ai D IN Standby/Write Inhibit V IH X (1)X X
High Z
Program Inhibit X X V IH Program Inhibit X V IL X Output Disable X
V IH
X
High
Z
Product Identification
Hardware
V IL V IL V IH
A1 - A18 = V IL , A9 = V H ,(3)
A0 = V IL
Manufacturer Code (4)
A1 - A18 = V IL , A9 = V H ,(3)A0 = V IH
Device Code (4)
Software (5)
A0 = V IL , A1 - A18 = V IL Manufacturer Code (4)A0 = V IH , A1 - A18 = V IL
Device Code (4)
DC and AC Operating Range
AT49BV/L V040-12
AT49BV/L V040-15
AT49BV/L V040-20
Operating
T emperature (Ca)Com.0°C - 70°C 0°C - 70°C 0°C - 70°C Ind.
-40°C - 85°C -40°C - 85°C -40°C - 85°C V CC Power Supply
2.7V to
3.6V/3.0V to 3.6V
2.7V to
个人借款模板3.6V/3.0V to 3.6V
2.7V to
3.6V/3.0V to 3.6V
DC Characteristics
Note:
1.
In the era mode, I CC is 50 mA.
Symbol Parameter Condition Min
Typ
Max Units I LI Input Load Current V IN = 0V to V CC 10µA I LO Output Leakage Current V I/O = 0V to V CC 10µA I SB1V CC Standby Current CMOS CE = V CC - 0.3V to V CC 50µA I SB2V CC Standby Current TTL CE = 2.0V to V CC
1mA I CC (1)V CC Active Current f = 5 MHz; I OUT = 0 mA, V CC = 3.6V
12
25mA V IL Input Low Voltage 0.8
V V IH Input High Voltage 2.0
V V OL Output Low Voltage I OL = 2.1 mA
0.45
V V OH Output High Voltage I OH = -100 µA; V CC = 3.0V
2.4V
元器件交易网
Input Test Waveforms and Measurement level t R , t F
< 5 ns
loudly
Output test Load
AC Read Waveforms (1)(2)(3)(4)
Notes: 1.CE may be delayed up to t ACC - t CE after the address transition without impact on t ACC .
2.OE may be delayed up to t CE - t OE after the falling edge of CE without impact on t CE or by t ACC - t OE after an address change without impact on t ACC .
3.t DF is specified from OE or CE whichever occurs first (CL = 5 pF).
4.
This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol Parameter
AT49BV/L V040-12
AT49BV/L V040-15AT49BV/L V040-20Units Min
Max Min
Max Min
Max t ACC Address to Output Delay 120150200ns t CE (1)CE to Output Delay 120150200ns t OE (2)OE to Output Delay 050070080ns t DF (3)(4)CE or OE to Output Float
030
040
050
ns t OH借古讽今的古诗
Output Hold from OE, CE or Address, whichever comes first
00
ns
Pin Capacitance
(f = 1 MHz, T = 25°C)(1)
Note:
1.
This parameter is characterized and is not 100% tested.
Typ
Max Units Conditions C IN 46pF V IN = 0V C OUT
8
红楼梦的艺术成就12
pF
V OUT = 0V
元器件交易网
