MIL-PRF-38534 QUALIFIED
FEATURES:
200V, 20 Amp Capability
Ultra Low Thermal Resistance - Junction to Ca - 1.0°C/W (Each MOSFET)Self-Contained, Smart Lowside/Highside Drive Circuitry Under-Voltage Lockout, Internal 2µS Deadtime Capable of Switching Frequencies to 25KHz Isolated Ca Allows Direct Heat Sinking
Ca Bolt-down Design Allows Superior Heat Dissipation
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DESCRIPTION:
The MSK 4322 is a 20 Amp, 3 Pha Bridge Smart Power Motor Drive Hybrid with a 200 volt rating on the output switches. The output switches are power MOSFETs with intrinsic fast-recovery diodes
for the free-wheeling currents of motor drives. This new smart power motor drive hybrid is compatible with 5V CMOS or TTL logic levels. The internal circuitry prevents simultaneous turn-on of the in-line half bridge transistors with a built-in 2µS deadtime to prevent shoot-through. Undervoltage lockout shuts down the bridge when the supply voltage gets to a point of incomplete turn-on of the output switches. The internal high-side boot strap power supply derived from the +15 volt supply completely eliminates the need for 3 floating independent power sup-plies for the high-side drive. Current n circuitry is provided to n current from an external resistor to shut down the bridge for overcurrent.
3 PHASE SIX STEP DC BRUSHLESS MOTOR DRIVE OR 3 PHASE SINUSOIDAL INDUCTION MOTOR DRIVE
12345678910
VCC AØHIN BØHIN CØHIN AØLIN FAULT CØLIN BØLIN VSS ITRIP
20191817161514131211
N/C AØV+N/C N/C BØN/C N/C CØCOM
查询MSK4322供应商
GROUP A SUBGROUP
5V+High 200V V CC Logic Supply ..........18V I OUT Continuous Output Current ...20A I PK Peak 30A θJC Thermal Resistance ......1.0°C/W (Output Switches) (Junction to Ca) Storage Temperature Range
Lead Temperature Range(10 Seconds) Ca Operating Temperature MSK 4322 MSK 4322H
水上世界Junction Temperature
1
员工管理制度Guaranteed by design but not tested. Typical parameters are reprentative of actual device performance but are for reference only.2Industrial grade devices shall be tested to subgroups 1 and
4 unless otherwi specified.3Military grade devices ("H" suffix) shall be 100% tested to subgroups 1, 2, 3 and 4.4Subgroups 5 and 6 testing available upon request.5
Subgroup 1, 4TA =TC =+25°C
2, 5TA =TC =+125°C 3, 6TA =TC =-55°C
Parameters
MSK 4322H Min. Typ. Max.
V+ = 200V V+ = 160V V+ = 200V
V CC = 15V V CC = 15V V+ = 100V, V CC = 15V, I D = 20A
V+ = 100V, V CC = 15V, I D = 20A -------------2.2----------300
2.05.0TBD 2.0TBD TBD 600750
3.0TBD 612TBD -0.8
TBD
TBD 45350TBD TBD 45350--
大虾炖白菜
-------------2.2----------300
-----------------------2-
2.0--2.0--600750--6---0.8
TBD TBD 45350TBD TBD 45350--
送桂州严大夫同用南字
MSK 4322Min. Typ. Max.UNITS OUTPUT CHARACTERISTICS
Rever Recovery Time
1
BIAS SUPPLY CHARACTERISTICS
告白日INPUT SIGNAL CHARACTERISTICS Positive Trigger Threshold Voltage Negative Trigger Threshold Voltage SWITCHING CHARACTERISTICS Upper Drive:Turn-On Propagation Delay Turn-Off Propagation Delay Turn-On Turn-Off Lower Drive:Turn-On Propagation Delay Turn-Off Propagation
Delay Turn-On Turn-Off Dead Time 1Minimum Pul Width 1
123123-1231231,2,31,2,3
----------
------------------------2-V V V V V V nS µA mA µA mA mA mA V V
nS nS nS nS nS nS nS nS µS nS
32
怎么哄女朋友睡觉Test Conditions
NOTES:
VDS(ON) (Each Transistor)
糖醋虾球Instantaneous Forward Voltage
(Intrinsic Diode)
Leakage Current
Quiescent Bias Current
V CC = 15V (non-switching)
I D = 20A
I S = 20A
1-65° to +150°C
300°C
-40°C to +85°C -55°C to +125°C +175°C
TsT TLD TC TJ
PROTECTION
-All logic inputs u a 300nS filter. A pul width below this will get ignored.
-VCC voltage below the cutoff level of 8.65 volts will ret all switch outputs off and ignore sub-quent logic inputs until VCC is restored.
-Undervoltage lockout of the internal drivers for the
high-side switches also occurs at 8.65 volts, but will not flag with the FAULT output. This may occur if the high-side output gets switched without switch ing the low-side. The interna l boot stra p power supply for the high-side switch will sag too low for adequate switching. The boot strap supply depends on PWMing of the low-side switches for proper opera tion.
-Switching a low-side logic input while the corre-sponding pha high-side logic input is a ctiva ted will turn off both switches. The opposite condition is a lso true. This is cross-conduction lockout a nd will occur a ny time low a nd high-side inputs for a ph a a re a ctiv a ted a t the s a me time.-A 2µS dea dtime is a utoma tica lly inrted between high a nd low-side output switching to a llow com-
plete turn-off of ea ch switch so no overla p will occur.
-An overcurrent condition detected by the ITR IP pin will shut down a ll output switches until the overcurrent condition is removed a nd a ll three low-side logic inputs a re held high for 10µS,
then normal operation will resume.
-ITRIP ha s a 100nS lea ding edge bla nking time a fter switching to ignore a ny switching current tra nsients.
TYPICAL OPERATION
MSK 4322 PIN DESCRIPTION
VCC - Is the low voltage supply for all the internal logic and drivers. A 0.1 µF ceramic capacitor in parallel with a 10µF tantalum capacitor is recommended bypassing for the VCC-VSS pins.
VSS - Is the low voltage supply return pin and the input logic return reference. All logic input and logic output is referenced to this pin. This pin can vary ±5V from the COM power return pin without affecting any of the logic functions.
AØHIN, BØHIN, CØHIN - Are low active logic inputs for signalling the corresponding pha high-side switch to turn on. The input levels are 5V CMOS or TTL compat-ible. Typica l propa ga tion dela ys a re a round 600nS.AØLIN, BØLIN, CØLIN - Are low active inputs for sig-nalling the corresponding pha low-side switch to turn on. The input levels are 5V CMOS or TTL compatible.Typica l propa ga tion dela ys a re a round 600nS.FAULT - Is a n open dra in logic output pin tha t gets enabled any time the VCC level goes below the cutoff point, or an overcurrent condition occurs. Bringing VCC back to normal levels will ret FAULT . Removing the overcurrent condition and allowing the low-side logic inputs to remain high(off) for 10µS will restore opera-tion.
ITRIP - Is an analog input pin for nsing current flow-ing from the COM pin through a n resistor to the high power ground. A 0.485 volt level at this pin with respect to VSS will signa l a n overcurrent condition,enable the FAULT pin and shut down all output switch-ing. Bringing the volta ge below this point (100 mV hysteresis) will remove the FAULT output and leaving the low-side logic inputs simultaneously high (de-acti-va ted) for 10µS will restore norma l opera tion.V+ - Is the high volta ge positive ra il for the bridge.Proper bypassing to VSS with sufficient capacitance to suppress any voltage transients and to ensure remov-ing any drooping during switching, should be done as clo to the pins on the hybrid a s possible - Is the return side of the bridge. A n resistor can be connected between this point and VSS , which is the high voltage negative rail. COM can float above and below the VSS pin up to 5 volts and proper opera-tion will be maintained. Precautions should be taken so as to not allow this voltage to get over ±5 volts under any conditions.
AØ, BØ, CØ - Are the pins connecting the 3 pha bridge switch outputs.
The MSK 4322 is designed to be ud with a +100 volt high voltage bus, +15 volt low power bus and +5 volt logic signals. Proper derating should be applied when designing the MSK 4322 into a system. High frequency layout techniques with ground planes on a printed circuit board is the only method that should be ud for circuit construction. This will prevent pul jitter caud by excessive noi pickup on the current n signal or the error amp signal.
Ground planes for the low power circuitry and high power circuitry should be kept parate. The connection between the bottom of the current n resistor, VSS pin and the high power ground are connected at this point. This is a critical path and high currents should not be flowing between the current n and VSS. Inductance in this path should be kept to a minimum. An RC filter (shown in 2 places) will filter out the current spikes and keep the detected noi for tho circuits down to a minimum.
In the system shown, two types of current limit are implemented. The first limit is a PWM pul by pul limit controlled by the motor controller. A cond absolute maximum limit is t up for the MSK 4322 which will completely shut off the bridge in the event that current limit is exceeded.
When controlling the motor speed by the PWM method, it is required that the low side switches be PWM puld due to the charge pump power supplies ud to power the high side switch drives. The higher the PWM speed the higher the current load on the drive supply. PWM of the low side will prevent sagging of the high side supplies. The logic signals coming from the typical motor controller IC are t up for driving N channel low side and P channel high side switches directly and are usually 15 volt levels. Provision should be made for getting 5 volt logic signals to the MSK 4322 of the correct asrtion levels. Typically, the low side signals out of the controller are high active and th
e high side are low active. Inverters are shown in the system schematic for the low side control-ler output.
