A CMOS HIGH-SPEED MULTISTAGE PREAMPLIFIER
FOR COMPARATOR DESIGN
X. P. Fan and P. K. Chan
Nanyang Technological University, School of Electrical and Electronic Engineering Block S1, Nanyang Avenue, Singapore 639798
ABSTRACT
A new multistage preamplifier with offt reduction for u in high-speed comparator is prented. The propod circuit is bad on the cascade of the modified input offt storage amplifiers and the output offt storage amplifier in pipeline arrangement. N ot only does the topology maintain a good input common-mode range, it exhibits faster speed due to reduced capacitive loads. Using AMS 0.35µm CMOS process model, the simulation result has shown that the new preamplifier has achieved a ttling time of 3.5 ns at 1% accuracy for a transient step of 400 mV, which is faster than the conventional works at identical process and identical power consumption.
1. INTRODUCTION
苏轼字体
In analog-to-digital converters, the comparator plays a crucial role on the overall performance. When dealing with high-speed applications, the comparator design tends to address simplicity in an architectural solution, which often compris a preamplifier followed by a latch [1],[3] as an example. The problems encountered by the comparator are therefore translated to the preamplifier specification and implementation, aiming at achieving good resolution, high sampling rate, low power consumption and small silicon area. Although a single amplifier stage [2] may meet certain constraints such as speed, power and area, it is also difficult to optimize accuracy among other performance parameters becau of finite gain and potential high input offt. As a conquence, this leads to the reported multistage preamplifier topologies [1],[4] incorporating the offt reduction technique. However, the well-known multistage preamplifier topologies have their distinct advantages for u in the comparators targeted for different application-specific ADCs. Despite the gain parameter and accuracy parameter have been improved as a common ultimate goal, there is also a penalty on the operation speed and exists other limitation in view of different architectures. Therefore, the objective of this paper is to investigate and to propo a new multistage preamplifier that alleviates the potential shortcomings from the previous works.
In ction 2, the operation principle of the prior-art circuits are described together with discussion on
the relative advantages and disadvantages. The propod circuit is detailed in ction 3. Finally, the results and discussions are prented in ction 4, which is then followed by the concluding remarks in ction 5.
2. MULTISTAGE PREAMPLIFIERS WITH
OFFSET REDUCTION
2.1. Multistage Preamplifiers wit h Input Offt
Storage
Fig. 1 illustrates a multistage preamplifier with input offt storage approach [1]. The structure is simple and it supports rail-to-rail common mode input. In the ret mode, the respective switch (S1, S2, S3) around each amplifier (A1, A2, A3) is clod, and the offt is stored on the respective capacitor (C1, C2, C3) in ries to the corresponding input. In the amplification mode, any difference between the sampled input and the reference voltage Vr is amplified by the gain, A v1A v2A v3, of the preamplifier. The effective input-referred offt can be derived as
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OSL
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where V OSL is the input offt of latch, V OS1, V OS2, V OS3 and A V1, A V2, A V3 are the respective input offt and voltage gain for the individual gain stage in the preamplifier.
As can be en from equation (1), the input-referred offt is reduced substantially via the product of three gain factors. However, the amplification pha is performed when all the feedback switches are off. It needs a long clock period becau a signal must be pasd through
three stages in half a clock period. Hence, the operation speed will be greatly limited by the effective
time constant of the complete amplifier. More importantly, when the active load, like CMOS inverter as an example, is utilized to implement the gain stage, the bandwidth will be reduced significantly.
Fig. 1 Input Offt Storage bad Multistage Preamplifier.The drawbacks can be overcome by the variant structure [4] as depicted in Fig. 2. The switch around amplifier is clod and opened alternatively between one amplifier and the next amplifier in pipelined operation. When stage 1 and stage 3 are in ret pha, stage 2 is in the amplification pha. When stage 1 and stage 3 are in amplification pha, stage 2 is in ret pha. In this pipeline operation, the difference between the sampled input and the reference voltage are amplified in the amplifier A 1 and stored in the capacitor C 2 with the ret-mode amplifier A 2, while the previous processing signal is transferred to the latch via the amplifier A 3 being arranged in switched-capacitor configuration.
Fig. 2 Pipeline Operation of Alternative Cascade Structure Despite the latency, this pipeline scheme is very effective for increasing the throughput becau the signal must be pasd through only one amplifier stage in half of the clock period. Since each gain stage is implemented by switched-capacitor technique [5], the gain factor, now defined by the capacitor ratio, is stabilized. However, the improvement of the amplifier time constant through the capacitor ratio is counteracted by the increa of capacitive loads via the illustration of all the capacitors (including parasitic capacitors) associated with the stage 1amplifier in Fig. 3(a).
(a) Stage1at Ret Pha and Amplification Pha
(b) Equivalent Circuit in Amplification Mode Fig. 3 Operation of Stage 1 Amplifier and Its Equivalent Circuit in Amplification Pha
Refer to Fig. 3(b), C 1X and C 1Y are parasitic capacitances at the input and output of stage 1 respectively. C 2X is the equivalent capacitance at the input of stage 2. From node X and Y, the time constant can be derived as [6]:m
Leq
m X amp G C G C C
11W (2)and the effective capacitive load at the output of A 1, node Y , is ]
/)(1)[//(111221f X X Y Leq C C C C C C C (3)
From equation (3), the amplifier time constant compris two time constant terms, the first term is proportional to input capacitance whilst the cond term is a linear function of effective capacitive load. It is important to note that the time constant can be reduced via increasing device conductance parameter but constrained by power and sizing budgets. The capacitive load depends on design parameter, but it is also linkage with the architecture. It can be en that high capacitive load would degrade the operation speed significantly.
2.2. Multistage Preamplifier wit h Output Offt
Storage A multistage preamplifier with output offt storage approach is shown in Fig. 4. In the ret mode, the respective switch (S 1, S 2, S 3 and S 4) is clod and hence the amplifier offts are stored on the respective output capacitor (C 1, C 2, C 3). In the amplification mode, any difference b
etween the sampled input and the reference voltage is amplified by A v1A v2A v3 times. The effective input-referred offt becomes
3
21V V V OSL
OS A A
A V V
(4)
To Latch
V in
V r
Vin
Vr
To
ret pha
amplification pha
where V OSL is the input offt of latch and A V1, A V2, A V3are the gain defined for the three amplifier stage respectively.
To Latch
V in
Fig. 4 Output Offt Storage bad Multistage
Preamplifier From equation (4), the input-referred offt is small.However, the input common-mode range is constrained by the direct input structure. Although this preamplifier would be faster than that of the input storage preamplifier due to abnce of input capacitor, the summed amplifier time constant limits the operation speed
3. NEW MULTISTAGE PREAMPLIFIER To improve the speed, a new multistage preamplifier bad on pipeline operation is shown in Fig. 5. The propod preamplifier has two different stages: (i) a modified input offt storage switched-capacitor amplifier for stage 1 and stage 3 and (ii) an output offt storage amplifier, implemented by a fully differential amplifier with passive load [6], for stage 2. The operation of the preamplifier together with the timing diagram is illustrated in Fig. 6.
Fig. 5 Propod Multistage Preamplifier
Fig. 6(d) shows the timing waveforms. In )1, stage 1 and
stage 3 are in amplification pha and stage 2 is in ret pha as depicted in Fig. 6(a). Two switches at the output of stage 2 clod in )1A are to speed up the ret of stage 2. Stage 1 amplifies the voltage difference at the sampled input and stage 3 amplifies voltage difference from the outputs of stage 2. In )2, stage 1 and stage 3 are in ret pha while stage 2 is in amplification pha as depicted in Fig. 6(b). Stage 2 amplifies the voltage difference from the outputs of stage 1. After )2 and before the start of )1, there is a small period )3 during which the feedback capacitors in stage 1 and stage 3 are discharged by
switches around them as shown in Fig. 6(c). The offts in stage 1 and stage 3 are reduced by means of input offt storage, whereas stage 2 utilizes the output offt storage technique to minimiz
e the offt storage as described before. From this operation, the total offt is also reduced substantially.
(a) At )1: Stage 1 and Stage 3 in Amplification Pha and Stage 2 in Ret Pha
(b) At )2: Stage 1 and Stage 3 in Ret Pha and Stage2 in Amplification Pha
(c) At )3: Ret Output Capacitors via Feedback
Switches
(d) Timing Diagram
Fig. 6 Timing Diagram for Operation of the Preamplifier The operation of switched-capacitor amplifier is different with that of the previous pipelined scheme. Fig. 7 shows the operation of stage 1 as an illustration example. The capacitor C 1f
粉黛万年青performs dual functions as a feedback capacitor in amplifying mode and as ac coupling capacitor in ret mode. When in amplification pha, the C 1f is also isolated from amplifier A 2. Therefore, less capacitive load appears at the output of amplifier A 1. Taken into the account of associated parasitic capacitors, the effective capacitive load is given as
V
V V r+V r-
3
)2
)1)A 1)V V V V To 2
)
]
/)(1[1111f X Y Leq C C C C C (5)
This is contrasting to previous scheme in Fig. 3(a), where the capacitor C 1f only functions as feedback element, and the amplifier A 1 drives the feedback capacitor C 1f and the
Fig. 7 Operation of Stage 1 in the Propod Structure Comparing equation (5) and equation (3), the capacitive load is smaller in the propod topology. Hence the amplifier time constant is reduced and faster speed can be attained whilst maintaining low offt performance.
4. RESULTS AND DISCUSSIONS
(a)First Stage Differential Output
(b)Second Stage Differential Output
(c) Third Stage Differential Output Fig. 8 Step Respons of the Three Preamplifiers
Three multistage topologies being designed with identical power consumption, on the basis of Fig. 1, Fig. 2 and Fig.5, were simulated using Level 49 BSIM3 models from the AMS 0.35P m CMOS process. All the gain stage amplifiers in the three designs are implemented using a common source amplifier [5] except the middle stage of the propod multistage amplifier, which utilizes a differential pair with passive load [6]. Fig. 8 shows the simulated results of different step respons at the respective differential output of each gain stage in the three multistage differential preamplifiers.
As can be en from the output waveforms, not only does the propod preamplifier exhibit higher sl
ew rate, it also achieves faster ttling characteristic due to the benefit of small capacitive load in reducing amplifier time constant.Compared with the ttling time among the structures I, II and III at 1% accuracy, the ttling times are obtained as 10ns, 5ns and 3.5ns, respectively, with no penalty for extra power consumption bad on the propod structure.It has confirmed that the propod preamplifier would offer an alternative structure for high-speed comparator design.
5. CONCLUSION
A low-offt high-speed multistage preamplifier with pipeline configuration is prented in this paper. Except with the slightly increa in complexity, the propod preamplifier is particular uful for high-speed comparator design with good resolution whilst offering a rail-to-rail input common mode range and maintaining identical power consumption with the prior-art multistage preamplifiers. Comparative simulations have validated the propod structure.
国考成绩什么时候公布REFERENCES
[1] B. Razavi and Bruce A. Wolley. “Design Techniques for High-Speed, High-Resolution Comparators,” IEEE J.of Solid State Circuits ,vol.27, pp. 1916-1926, Dec. 1992.[2] B. Razavi, Principles o f Data Co nversio n System Design , IEEE Press, 1995.
[3] Gustavsson,Wilner and Tan,. CMOS Data Converters for Communications , Kluwer Academic Publishers, 2000.[4] K. Kusumoto and A. Matsuzawa, “A 10-b 20-MHz 30-mW Pipelined Interpolating CMOS ADC,” IEEE J.Solid-State Circuit s, vol. 28, pp. 1200–1206, Dec. 1993.[5] R. C. Taft and M. R. Tursi, “A 100-MS/s 8-b CMOS Subranging ADC with Sustained Parametric Performance from 3.8V Down to 2.2V,” IEEE J. So lid-State Circuit s,vol. 36, pp. 331–338, March 2001.
[6] B. Razavi, Design o f Analo g CMOS Integrated Circuits , McGRAW-Hill, 2001.
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