Thermometer-to-Binary Decoders for Flash Analog-to-Digital
Converters
Erik S¨a ll and Mark Vesterbacka
Department of Electrical Engineering,Link¨o ping University
SE-58183Link¨o ping,Sweden
Email:eriks,markv@isy.liu.
Abstract—Decoders for low power,high-speedflash ADCs are investi-gated.The nsitivity to bubble errors of the ROM decoder with error cor-rection,ones-counter,4-level folded Wallace-tree,and multiplexer-bad decoder are simulated.The ones-counter and multiplexer-bad decoder, corresponding to the error innsitive and hardware efficient cas,are implemented in a130nm CMOS SOI technology.Measurements yield an ENOB of about4.1bit for both,and energy consumption of80pJ and60 pJ,for the respective decoders.Hence we conclude that the MUX-bad decoder ems to be a good choice with respect to area,efficiency,and speed.
I.I NTRODUCTION
Applications like ultra-wideband radio and the read channel in hard disk drives generally require high-speed analog-to-digital conversion with resolution four to six bits.The requirements are commonly satisfied by theflash analog-to-digital converter(ADC)architecture [1]that converts the analog input to a binary output with a single stage of2N−1parallel comparators,where N is the number of bits in the output,followed by a digital decoder.The comparators compare the input with the quantization levels from a t of reference voltages generated by a resistive ladder and produce a logical output depending on the outcome of the comparison.The output pattern from this stage corresponds to thermometer code and is subquently translated to binary code by the digital he thermometer-to-binary decoder.For a low speed converter the input to the decoder is indeed a perfect thermometer code,but for high speed there may be some erroneous bits in the thermometer code,so called bubbles[2].The bubbles are due to a number of sources[3],e.g.,metastability,offt, crosstalk,and bandwidth limitations of the comparators,uncertainty in the effective sampling instant,etc.Hence the decoder must be able to perform well even in the prence of the bubble errors in a high-speed converter.Including requirements on power consumption and throughput,we e that the decoder must be paid significant consideration and trade-off in the design of a high-speed converter. In this work we focus on the design of decoders for low-power, high-speed six-bit ADCs.The work is a part of a larger proje
ct where the overall aim is to develop design techniques for implementation of high-performance analog circuits in CMOS silicon-on-insulator technology.We have investigated four types of thermometer-to-binary decoders prented in Sec.II,through behavioral level simulations of the nsitivity to bubble errors prented in Sec.III,from which we have chon two decoders that have been implemented in a130 nm CMOS SOI technology.The measurement results are prented in Sec.IV and the conclusions are given in Sec.V.
II.D ECODERS
Four different types of thermometer-to-binary decoders are pre-nted.Two of them,the ROM and folded Wallace tree decoder, are only studied on behavioral level.The ones-counter decoder and the MUX-bad decoder have also been implemented in twoflash ADCs in a CMOS silicon-on-insulator technology.The corresponding results are thereby bad on transistor level simulation results and measurements.
A.ROM
A common and straightforward approach to encode the thermome-ter code is to u a gray or binary-encoded ROM.The appropriate row m in the gray encoded ROM is lected by using a row d
ecoder that has the output of comparator m and the inver of comparator m+1as inputs.The output m of the row decoder,connected to memory row m,is high if the output of comparator m is high and the output of comparator m+1is low.The row decoder can be realized ,a number of2-input NAND gates,where one input to each NAND gate is inverted.This type of row decoder lects multiple rows if a bubble error occurs,which introduces large errors in the output of the decoder[3],[4].Considering single bubble errors only,the errors can be corrected by using3-input NAND gates,as shown in Fig.1.The3-input NAND gates remove all bubble errors if they are parated by at least three bits in the thermometer scale. The main advantage of the ROM decoder approach is its regular structure that is straightforward to design.A disadvantage is that more bubble errors are introduced as the conversion speed increas and a more advanced bubble error correction scheme is required. As the complexity of the bubble error correction circuit increas, its propagation delay does in general also increa.The longer propagation delay reduces the maximum sampling rate of the overall decoder if not pipelining is applied.The incread complexity of the circuit consumes more chip area and will likely consume more power[5],[6].
R
R
R
R
N 1
0 Fig.1.Illustration of aflash ADC with gray encoded ROM decoder.
Another bubble error suppression technique is the butterfly sorting technique prented in [7].Applying this technique the bubbles are propagated upwards in the thermometer scale until the thermometer code is free from bubbles.Then the ROM decoder is ud to encode the bubble-free thermometer code to binary code.In [7]the butterfly sorter only has eight levels.Bubbles further away from the transition level than eight positions cannot be removed.To guarantee that no bubbles will be prent in the thermometer output code the depth of the butterfly sorter must be equal to the number of ,2N −1.B.Ones-Counter
The output of a thermometer-to-binary decoder is the number of ones on the input reprented ,gray or binary code.Hence a circuit counting the number of ones in the thermometer ,a ones-counter,can be ud as the decoder [8].
The u of a ones-counter gives global bubble error suppression [3],[6],[8].Another benefit of the approach is that a suitable ones-counter topology may be lected by trading speed for power.From this trade-off the Wallace tree topology [9],illustrated in Fig.2,is a good candidate as a decoder for high-speed converters [3],[6],[10].
2N 2N m
1
23Fig.2.
Wallace tree decoder for an N =4-bit flash ADC.
In this work we u a tree of full adders (FAs)that reduce the 63inputs to 10outputs,as illustrated by Fig.3.The different signal paths through the decoder are ,each signal pass through the same number of full adders,where each input has approximately the same propagation delay to the
output.The propagation delay of the signals through the decoder should thereby be approximately the same for all signals.
The decoding of the 10outputs to the binary value is done using MATLAB.The depth of the tree is thereby limited to six levels in the hardware implementation prented in the next ction,which enables the ADC to operate at higher speed.In an improved design the complete decoding to a binary output can be accomplished on-chip by introducing pipelining in the decoder.Further optimization of the sizing of each FA can also improve the performance to some degree.
续母C.Folded Wallace Tree
In a folded flash ADC,the idea is to reduce the amount of hardware by using the same comparator for different reference voltages [11].This is the idea of the folded Wallace tree decoder shown in Fig.4[6].The size of the Wallace tree and the delay depend on the number of bits that are he width of the ba of the tree.The idea is to split the output of the comparators into different intervals.They
On-chip decoder
Fig.3.Illustration of the ones-counter decoder.
are multiplexed to a reduced Wallace tree decoder,which is smaller compared with the full one [3].A full adder may be realized from three 2:1multiplexers with two multiplexers in the critical path.
2N
原单是什么意思(2k 1).22.222 1
10
k
k +1
Fig.4.Illustration of the folded Wallace tree decoder.
D.MUX-Bad
The multiplexer-bad decoder consists entirely of multiplexers,as illustrated in Fig.5,where N =4bit.It requires less hardware and has a shorter critical path than a ones-counter decoder [3],[5].In addition it gives bubble error suppression,although the suppression is slightly lower than for a ones-counter decoder [5].Another advantage of the multiplexer-bad decoder is the more regular structure ,the ones-counter decoder.This is a major benefit in the layout of the circuit.The multiplexers ud in this work are bad on transmission gates.An inverter is ud as a buffer in each transmission gate multiplexer.
III.B EHAVIORAL L EVEL S IMULATION
The effect of the chon decoder topology on the ADC perfor-mance was evaluated by behavioral level simulations for the four different architectures.The timing difference ∆t between the clock signal and the input signal to each comparator was modeled by a Gaussian distribution,according to
∆t ∼N (0,σt ).
(1)
The timing difference is of concern if no sample-and-hold circuit is ud,which is acceptable for converters with a resolution less than 6
b 0b 1
b 2
b 3
Fig.5.
Multiplexer-bad decoder for N =4bits.
bits [12].The timing difference mismatch between the comparators introduces bubble errors.The bubble errors have significant effect on the ADC ,in terms of effective number of bits (ENOB).The performance of the decoders can thereby be compared by plotting the ENOB as a function of the standard deviation σt .A MATLAB model was developed to enable the performance comparison.In the behavioral level simulations a single tone sinusoid input were assumed according to
V in =
溥仪皇帝V FS
发挥英文
2
sin (2πf in t ),(2)
where V FS is the full-scale voltage.An approximation of the maxi-mum time derivative of the input is
∆V in
∆t
≈max ˛
˛˛˛dV in dt ˛˛˛˛ff=πf in V FS .(3)The effect of the timing difference is therefore an uncertainty in the sampled input voltage,∆V in .Using (3),the maximum uncertainty in the sampled input voltage has a Gaussian distribution according to
∆V in ∼N (0,σt p
πf in V FS ).(4)
The uncertainty ∆V in is added to the input V in in the simulations.
The sampling time uncertainty is therefore modeled as an offt voltage on the input of the comparators,given by (4).This model was ud in the MATLAB simulations of a flash ADC with the four
different ,the ROM decoder with 3-input NAND gates for bubble error correction,the ones-counter decoder,the MUX-bad decoder,and the 4-level folded Wallace tree decoder.The results of the simulations are shown in Fig.6.
生日游戏In Fig.6the average ENOB of a 6-bit ADC is plotted as a function of the standard deviation of the timing difference between the clock lines and the signal ,σt .As en in the figure the performance of the MUX-bad decoder is about the same as for the ROM decoder with 3-input NAND gates ud for the bubble error correction.Note that the MUX-bad decoder has no special bubble error correction circuits.It is also en that the ones-counter decoder
has better performance than both the ROM decoder and the MUX-bad decoder.Finally,the 4-level folded Wallace tree decoder has a slightly lower average ENOB than the ones-counter.The reason for this is that the folded Wallace tree topology is more nsitive to bubble errors at the thermometer input levels that are connected to the 3-input OR gates shown in Fig.4,since the levels control the MUX en in the same figure.
Fig.6.Average ENOB as a function of σt for the ROM decoder with 3-input NAND gates,the ones-counter decoder,the MUX-bad decoder,and the 4-level folded Wallace tree decoder.
IV.M EASUREMENT R ESULTS
From the behavioral simulation we saw that the ones-counter decoder was the most innsitive to bubble errors.Of the other decoders,the MUX-bad stands out as having the lowest hardware cost,but a somewhat higher nsitivity to bubble errors.We choo the two decoders for hardware implementation in 6-bit,1-GHz ADCs in a 130nm CMOS silicon-on-insulator technology.To save power,a sample-and-hold circuit is avoided in the design [12],and the decoders are implemented without pipelining.To avoid excessive delay in the ones-counter decoder the adder tree is only partially im-plemented.Hence six more full adders are required,who operation instead are perform
ed through postprocessing in MATLAB and their contribution to the power consumption is extrapolated.The total chip areas are 4.1mm 2and 2.9mm 2,and the core areas are 0.7mm 2and 0.4mm 2for the ones-counter and MUX-bad ADCs,respectively.The dynamic performance is evaluated by applying a single tone sinusoidal input to the ADC and obtaining its spectral measures from a plot of the output spectrum.An estimate of the maximum sampling frequency,f s,max ,is first derived.With a low frequency (495kHz)sinusoidal input the sampling frequency is swept from 7MHz up to sampling frequencies above 1GHz.However,the ud measurement equipment only allowed sampling of the output at a few discrete time instances relative to the clock,which limited the measurements to only be accurate within time periods where the sampling and the stable output could be made coincidental.
The result of the measurements for the ones-counter ADC is shown in Fig.7,where the SNDR is plotted as function of the sampling frequency.The maximum SNDR is 26.3dB,which is equivalent to an ENOB of about 4.1bit.The performance degradation in the frequency range from 500MHz to about 900MHz is believed to mainly be due to the sampling instant being too clo to the switching events of the output,limited by the ud measurement equipment.
Fig.7.The measured SNDR of the ones-counter ADC with a sinusoidal input of frequency f in=495kHz as a function of the sampling frequency. At an input frequency of120MHz and a sampling frequency of 440MHz,an SFDR of28.7dB is obtained.The power consumption of the ADC is then175mW,excluding the power consumption of the input and output buffers.Including the power consumption of the buffers the total power consumption becomes312mW.The contribution from the digital part is about70%of the total power consumption,excluding the input and output buffers.The results indicate an energy consumption per conversion step of about80pJ.
除虫The delay through the MUX-decoder will vary depending on data. To investigate the delay,the time from the rising edge of the clock on the clock input to the output change is measured.This measurem
ent gives the delay through an input buffer,a clock buffer,a Dflip-flop,a MUX-decoder,and an output buffer.The delay for the’0’to’1’transition is measured by applying a high input voltage to ensure that all comparator outputs always are logic one.Between the measurements there is a Dflip-flop on each comparator output that is ret and the ret signal is relead before the Dflip-flops are triggered by the clock.Hence the ADC outputs are all zero.When the clock triggers the Dflip-flops on the rising edge their outputs become logic one and the ADC outputs goes from logic zero to logic one.A similar method is ud to measure the’1’to’0’transition.The result of the measurements showed that the delay from the ADC clock input to the ADC output bits is in the range from2.8ns to3.2ns.Hence the data dependent variation of the delay should be acceptable at the sampling frequencies ud in this work.However,the variation does further complicate measurement with the ud equipment.As in the ca with the ones-counter ADC the500-900MHz region is problematic,and in addition we do also have a more distributed error over the frequencies due to the delay variation.In retrospective, we e that pipelining probably is needed if the decoders should be usable for a wide range of sample frequencies.
The corresponding result of the measurements of the dynamic performance for the MUX-bad ADC is shown in Fig.8,where the SNDR is plotted as a function of frequency.For an input frequency of120
MHz and a sampling frequency of440MHz,an SFDR of29.9dB is obtained.The power consumption is then182mW, excluding the power consumption of the input and output buffers. The power consumption of the analog part is55mW.The power consumption including the input and output buffers are271mW. The results indicate an energy consumption per conversion step of about60pJ.
Fig.8.The measured SNDR of the MUX-bad ADC with a sinusoidal input of frequency f in=495kHz as a function of the sampling frequency.
V.C ONCLUSIONS
Implementation and measurement of two6-bit1-GHz ADCs with different thermometer-to-binary enco
ders show that a MUX-bad decoder is more efficient in terms of power consumption and has about40%smaller chip area than a ones-counter decoder.We saw that pipelining of the decoders probably is needed if they are to be ud for a wide range of sample frequencies.For the MUX-bad decoder there was also a significant data dependent delay spread of the output bits of the MUX-bad decoder that will limit its maximum speed for high frequencies.Hencefinding ways to reduce the spread would make the MUX-bad decoder promising for future designs.
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