Probing an ECLcircuit with ries termination using a passive probe (trace T3 and T4) and an active FET probe
(traces T1 and T2).
Introduction
High-performance logic fami-lies have pushed the world of CMOS and ECL into the picocond realm. When out-put transitions move into this time domain, it becomes necessary to critically ana-lyze signal measurements made with a probe.
Oscilloscope urs need to consider the questions: •How much, if any, does probe input capacitance affect the measured signal? •How much capacitance can be tolerated? Do I need to be concerned about this? Selecting a probe with the right capacitance will signifi-cantly improve measurement accuracies.
Most digital and analog designers agree that an
increasingly important con-sideration in lecting a
probe is capacitance. The ca-pacitance of the probe or fix-ture adds to the load of the device-under-test (DUT) and can cau the ritime to be degraded or induce aberra-tions such as ringing in the acquired signal. In cas
where high-impedance prob-ing is required due to circuit loading considerations,probe capacitance is espe-cially important. Probe ca-pacitance not only loads the circuit, but it increas the need for careful grounding.Just as bandwidth and ri-time of an oscilloscope can have a significant impact on making accurate timing and
Copyright © 1996 Tektronix, Inc. All rights rerved.
amplitude measurements,capacitance of a probe can substantially alter a mea-sured waveform’s ritime and waveshape. In digital systems, clock rate is not the determining factor of the scope’s bandwidth require-ment. Clock rate is not the critical determinant in
choosing probe input capaci-tance values either. Instead,the ri and fall times of the signals to be measured are the appropriate factors for lecting both the scope bandwidth and probe input capacitance.
It’s important to keep in mind the relationship between ritime (tr) and bandwidth when you are choosing an oscilloscope and/or probe to make preci timing measurements:
b w ( – 3 d B )≈ 0.35/t r
Similarly, probe input capac-itance directly influences the fastest signal components within the DUT. Don’t u the clock rate as the deter-mining component for choos-ing input capacitance of a probe, since it’s usually much lower than the band-width of the signals due to their fast edges. Work station computers, for example,which often employ Ad-vanced CMOS logic running at clock rates up to 300MHz usually have signal ri times with bandwidths of 700MHz and more.
For additional information on making an informed choice about oscilloscope and/or probe bandwidth as it relates to measurement error,obtain a copy of Tektronix technical brief 85W-8907-0,“The Effect of Bandwidth on
The Effect of Probe Input Capacitance On
Measurement Accuracy
Technical Brief
Measurement Accuracy ” and technical brief 60W-8412-1,“Probing High Frequency Digital Circuitry ”.
The Effect of Probe Input Capacitance
When the load capacitance of the probe you are using is significant compared to the capacitive load the DUT is designed to drive, your
chance of making an accurate measurement is substantially reduced. Remember that the
total capacitive loading for a DUT is a combination of the designed-for capacitive
fanout, environmental capac-itance, and the probe input capacitance. The ratio of the probe capacitance to the DUT capacitance alters the origi-nal waveform geometry in both the vertical axis as well as the horizontal axis by that ratio.
The DC loading fanouts for logic circuits are computed by dividing the output cur-rent by the input current.However, both AC limita-tions and current needed in the output termination can be expected to restrict the DUT fanout to a smaller number than the one com-puted. If the maximum num-ber of permissible fanout
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loads are not exceeded by the addition of some amount of probe input capacitance
beyond a good safety margin,
then it’s safe to assume that the probe will not apprecia-bly invade the DUT out-put wave-form. And,correspond-ingly, the measured waveform accurately reprents the DUT out-put as if the probe capac-itance were not there.This is the ideal ca.The digital designer must verify that probe input capaci-tance is within the device
fanout load specification and, there-fore, caus minimum signal distor-
tion and maximum signal fidelity.
Table 1 shows the equivalent bandwidth for typical output ritimes from veral fast logic families in addition to typical gate input capaci-tance values.
Digital circuit designers have a choice between transmis-sion lines and conventional interconnect wiring when distances between gate devices are short. But what about adding the input capacitance of a probe to the high-speed circuits for device characterization or device testing purpos? The design decision must take into consideration additional lumped capacitance. Incor-rect lection of
measure-ment probe capacitance val-ues could result in fal sys-tem operation due to a high percentage of incident pul reflections and subquent lowering of the AC noi im-munity. The basic factors which will affect this design decision are:
•System ritime
•Interconnect distance
•Capacitive loading (fanout plus probe lumped capaci-tance)
•Resistive loading (line ter-mination)
•Percentage of undershoot and overshoot permissible (reduction in noi immu-nity)F i g u r e 1 reprents a typical ECL logic circuit for the pur-po of analyzing the degree of measurement error intro-duced by the probe. Remem-ber that probe loading effects on a DUT become more pro-nounced as signal edge
speeds get faster and propaga-tion delay times become shorter. The variation of sig-nal propagation times through a fast logic family versus the number of load gates is typi-cally designed to meet very stringent system operating re-quirements in speed, skew,and circuit density.
Figure 3. Thevenin equivalent models of Figure 2.
桉树用途Figure 2. ECLip transmission line equivalent model.
Figure 1. A typical ECLip digital circuit.
Table 1. Typical Logic Technology Ritimes and Equivalent Bandwidths with Typical
Gate Input Capacitance
Logic Typical Bandwidth
Gate Input CMOS 1.5 nc 230 MHz 5 pF Advanced CMOS 800 pc
440 MHz 3 pF ECL 500 pc 700 MHz 3 pF ECLip 300 pc 1.17 GHz 1.4 pF GaAs
100 pc
3.5 GHz
1.5 pF
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load C t . Figure 3a and 3b illustrate Thevenized ver-sions of Figure 2.
成长别烦恼The capacitive load, C t rves to reprent the DUT input capacitance plus any other capacitance that may prent itlf at the v out node. Propa-gation delay increas
through the transmission line may now be determined by changing Figure 3b into a simple time constant circuit with a time constant t c and a
ries im-pedance Z t .Under a no-load state, C t =0, the sig-nal delay between the 50%-point of the input waveform and the
50%-point of the output waveform, is defined as the line delay, t pd .See Figure 4.The capaci-tive load from a probe added to the end of the transmission line slows down the output signal ritime,thereby in-creasing t pd by the
amount ∆t pd .Figure 5shows the increa in respon delay for veral dif-ferent probe input capaci-tance loads. The increa in signal ritime and signal delay as a function
of additional lumped capaci-tance can be determined by the delay change and the time constant of the trans-mission line load. Figure 6shows the relationship be-tween the transmission line load time constant and the resulting change in delay.This diagram gives a conve-nient graphical approxima-tion for determining
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increas in signal delay as a function of additional
lumped capacitive loads. The following example rves to illustrate the ufulness of the diagram.
Referring back to Figure 2,the transmission line is par-allel terminated by 50Ω driv-ing an incremental 2pF
probe input capacitance load with a no-load ritime of 300 pc. The delay increa factor is determined by Fig-ure 6. The transmission line load time constant is expresd by:
Ro *C t /t r
Where:
R o =Z o .
So:
R o C t /t r = (50)(2 E-12)/300E-12) = 0.33
Using this result and Figure 6, the transmission line load delay factor equals 0.36. Therefore:
∆ t p d = (0.36)(300 pc) = 108p s e c
The 108pc is added to the no-load transmission line ritime to arrive at the ap-proximate delay caud by a 2pF lumped load at the out-put of the line. The 2pF lumped capacitive load rep-rents the incremental load of a medium performance active FET probe when ud to pick off the digital signal at the point of interest. Table 2 shows the percent of mea-surement error introduced by a ries of high-performance probes with different input capacitance values.
The output waveform at the end of a parallel-terminated transmission line, shown as v l o a d in Figure 1 can be derived from an equivalent circuit using Thevenin’s The-orem. Figure 2 shows the par-allel-terminated transmission line circuit, along with the waveform driving the line.Notice the transmission line is parallel terminated by Zo to ground with a capacitive
Figure 6. Signal delay increas as a function of probe input.
Figure 4. ∆t pd Introduced by the input capacitance of a measurement probe load.
Figure 5. Effect of probe input capacitance on typical ECLip logic signal ritime.
Conclusion
The effect of probe input ca-pacitance on signal ritime and propagation delays must be considered when lecting a probe for u with high performance integrated cir-cuit logic technologies, such as Advanced CMOS, Fast
迎合的近义词ECL (e.g., ECLip), and斯诺克彩球顺序
GaAs. The increa in propa-gation delay can be found by Theveninizing the DUT and converting the equivalent to a single time constant circuit with a step-function input voltage with a finite ritime voltage.
Thus, when critical delay paths and ritimes are being designed it must be compul-sory for the designer to give special forethought to the cir-cuit termination scheme and the method by which sign
als may be acquired with mini-mal impact to the optimiza-tion of the signal delay and ritime performance.
Therefore, the effect of incre-mental probe input capaci-tance on typical high-perfor-mance logic family gate-to-gate signal delay and ri-time is to increa the propa-gation delay and slow down the signal ritime. To obtain the least measurement error and lowest propagation delay as a function of probe load-ing, the lowest characteristic probe input capacitance should be ud.
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